Abstract
Network-on-chip (NoC) has been introduced to increase the performance of chip multiprocessors (CMPs) and execute parallel programs. Although NoC is known as a modular and scalable infrastructure for interconnections, there are still some challenges with conventional NoC such as high latency and power consumption due to the communication among long-distance (LD) cores. In this regard, wireless network-on-chip (WiNoC) is a potential solution that can provide high bandwidth and low latency by means of the unique features of wireless interconnects. However, wireless routers (WRs) are prone to congestion in WiNoC due to the limited number of wireless channels on a chip and shared use of these channels by all processing elements (PEs). In this study, a load-balanced time-based congestion-aware (LTCA) routing algorithm is proposed to eliminate the congestion of WRs and distribute the traffic load on the wired and wireless networks in a balanced way. LTCA is a deadlock-free routing algorithm in which only a limited number of packets are allowed to use wireless channels. The required time for transmitting the selected packets through wireless links is measured with regard to the bandwidth of the wireless channels and traffic load. Simulation results on synthetic traffic patterns and real-world 3-tuple traffic patterns indicated a considerable improvement in latency, throughput, wired and wireless link utilization and packet loss probability.
Published Version
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