De-embedding Technique Research Articles

A De-Embedding Technique of a Three-Port Network with Two Ports Coupled

A de-embedding method for multiport networks, especially for coupled odd interconnection lines, is presented in this paper. This method does not require a conversion from S-parameters to T-parameters, which is widely used in the de-embedding technique of multiport networks based on cascaded simple two-port relations, whereas here, we apply an operation to the S-matrix to generate all the uncoupled and coupled coefficients. The derivation of the method is based on the relations of incident and reflected waves between the input of the entire network and the input of the intrinsic device under test (DUT). The characteristics of the intrinsic DUT are eventually achieved and expressed as a function of the S-parameters of the whole network, which are easily obtained. The derived coefficients constitute ABCD-parameters for a convenient implementation of the method into cascaded multiport networks. A validation was performed based on a spice-like circuit simulator, and this verified the proposed method for both uncoupled and coupled cases.

Radio Frequency Transistors and Circuits Based on CVD MoS2.

We report on the gigahertz radio frequency (RF) performance of chemical vapor deposited (CVD) monolayer MoS2 field-effect transistors (FETs). Initial DC characterizations of fabricated MoS2 FETs yielded current densities exceeding 200 μA/μm and maximum transconductance of 38 μS/μm. A contact resistance corrected low-field mobility of 55 cm(2)/(V s) was achieved. Radio frequency FETs were fabricated in the ground-signal-ground (GSG) layout, and standard de-embedding techniques were applied. Operating at the peak transconductance, we obtain short-circuit current-gain intrinsic cutoff frequency, fT, of 6.7 GHz and maximum intrinsic oscillation frequency, fmax, of 5.3 GHz for a device with a gate length of 250 nm. The MoS2 device afforded an extrinsic voltage gain Av of 6 dB at 100 MHz with voltage amplification until 3 GHz. With the as-measured frequency performance of CVD MoS2, we provide the first demonstration of a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of -15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications.

On-wafer de-embedding techniques from 0.1 to 110 GHz**Project supported by the National Natural Science Foundation of China (No. 61401457).

On-wafer S-parameter de-embedding techniques from 0.1 to 110 GHz are researched. The solving results of thru-reflect-line (TRL) and line-reflect-match (LRM) de-embedding algorithms, when the input and output ports are asymmetric, are given. The de-embedding standards of TRL and LRM are designed on an InP substrate. The validity of the de-embedding results is demonstrated through two passive components, and the accuracy of TRL and LRM de-embedding techniques is compared from 0.1 to 110 GHz. By utilizing an LRM technique in 0.1–40 GHz and a TRL technique in 75–110 GHz, the intrinsic S-parameters of active device HBT in two frequency bands are obtained, and comparisons of the extracted small-signal current gain and the unilateral power gain before and after de-embedding are presented. The whole S-parameters of actual DUT from 0.1 to 110 GHz can be obtained by interpolation.

1 to 220 GHz Complex Permittivity Behavior of Flexible Polydimethylsiloxane Substrate

Coplanar transmission lines (CPW) are realized on polydimethylsiloxane (PDMS) substrate in order to characterize its complex permittivity, from 1 to 220 GHz. By varying the complex permittivity, the propagation constant of the PDMS-CPW calculated with full wave software is matched to those extracted by de-embedding techniques using S-parameters measurements. The real permittivity evolves from 2.9 to 2.55 while the loss tangent increases slowly to reach 0.048 at 210 GHz.

Accuracy of Microwave Transistor $f_{\rm T}$ and $f_{\rm MAX}$ Extractions

We present a complete methodology to evaluate the accuracy of the microwave transistor figures-of-merit f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> (current gain cutoff frequency) and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> (maximum oscillation frequency). These figures-of-merit are usually extracted from calibrated S-parameter measurements affected by residual calibration and measurement uncertainties. Thus, the uncertainties associated with f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> can be evaluated only after an accurate computation of the S-parameters uncertainties. This is done with the aid of two recently released software tools. In the uncertainty propagation, the standard de-embedding techniques are assumed to be error free, but still contribute to the final uncertainty budget via their measurement uncertainty. We also present an analysis of how different interpolation/extrapolation methodologies affect uncertainty. In addition, an overview of the possible causes of errors and suggestions on how to avoid them are given. With the continued rise of reported f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> values, this work has become necessary in order to evaluate the accuracy of these figures-of-merit both by adding confidence intervals to their values and by identifying possible extraction errors.

Modeling and parameter extraction of CMOS on-chip coplanar waveguides up to 67 GHz for mm-wave applications

Coplanar waveguides (CPW) are widely used in mm-wave circuits designs for their good performance. A novel unified model of various on chip CPWs for mm-wave application, together with corresponding direct parameter extraction methodologies, are proposed and investigated, where standard CPW, grounded CPW (GCPW) and CPW with slotted shield (SCPW) are included. Several kinds of influences of different structures are analyzed and considered into the model to explain the frequency-dependent per-unit-length L, C, R, and G parameters, among which the electromagnetic coupling for CPWs with large lower ground or shield is described by a new C–L–R series path in the parallel branch. The direct extraction procedures are established, which can ensure both accuracy and simplicity compared with other reported methods. Different CPWs are fabricated and measured on 90-nm CMOS processes with Short-Open-Load-Through (SOLT) de-embedding techniques. Excellent agreement between the model and the measured data for different CPWs is achieved up to 67 GHz.

A Distributed De-Embedding Solution for CMOS mm-Wave On-Wafer Measurements Based-on Double Open-Short Technique

In this letter, a novel distributed de-embedding solution with double open-short structures are proposed and investigated. The distributed effect is well considered by regarding the interconnection as scalable transmission line at high frequency and all the parasitic parameters can be extracted directly by three steps. Experimental results show this general distributed de-embedding technique provides more stable on-wafer parasitic extraction than well-adopted SLOT de-embedding technique at millimeter-wave frequency.

THRU-Based Cascade De-embedding Technique for On-Wafer Characterization of RF CMOS Devices

In this paper, an accurate two-port cascade-based de-embedding technique is presented for characterization of RF devices. It uses two and four structures for device structure with symmetrical and asymmetrical layouts, respectively. Specifically, it outperforms the existing de-embedding techniques by showing distinct capability of accounting for both series contact resistance and distributed effects of interconnects. Furthermore, it is designed to overcome the deficiency of existing transmission line-based techniques in dealing with the interconnects of nonuniform line width. To avoid over de-embedding errors in lumped techniques, the deembedding is performed in unique steps with solely THRU structures for better prediction of test fixture parasitic. The proposed technique is verified on THRU line for a wide frequency range from 2 to 50 GHz. It demonstrates better performance over existing transmission line-based technique as evidenced by excellent agreement with electromagnetic simulation result of THRU line. This is further confirmed by validation result on deembedded gain and gate capacitance of 0.13-μm nMOS devices.

De-Embedding 기술을 이용한 IC 내부의 전원분배망 추출에 관한 연구

IC 내부의 전원분배망(PDN: Power Delivery Network) 회로를 분석하기 위해서는 IC의 디자인 정보가 담긴 파일이 필요하지만, 상용 IC(Commercial IC)의 경우 보안상의 이유로 디자인 정보를 제공하지 않고 있다. 하지만 온-칩 전원분배망(On-chip PDN) 특성이 포함된 경우에는 PCB와 패키지의 특성만으로는 정확한 해석이 어려우므로 본 연구에서는 IC 내부의 정보가 제공하지 않는 전원분배망(PDN) 회로의 추출에 관하여 연구를 하였다. IC 내부의 전원분배망(PDN)의 주파수에 대한 특성을 추출하기 위하여, IEC62014-3에서 제안하고 있는 추출용 보드를 제작하였고, 추출용 보드를 구성하고 있는 SMA 커넥터, 패드, 전송 선로, 그리고 QFN 패키지의 주파수에 대한 특성들을 분석하였다. 추출된 결과들은 디임베딩(de-embedding) 기술에 적용하여 IC 내부의 전원분배망(PDN) 회로를 S-parameter 기반으로 모델을 추출하였고, 평가용 보드의 전원분배망 결합회로(PDN Co-simulation)모델에 적용하여 측정과 비교한 결과, ~4 GHz까지 잘 일치하였다. GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.

In Situ Measurement of Tissue Impedance Using an Inductive Coupling Interface Circuit

In this work, a method of an inductive coupling impedance measurement (ICIM) is proposed for measuring the nerve impedance of a dorsal root ganglion (DRG) under PRF stimulation. ICIM provides a contactless interface for measuring the reflected impedance by an impedance analyzer with a low excitation voltage of 7 mV. The paper develops a calibration procedure involving a 50-Ω reference resistor to calibrate the reflected resistance for measuring resistance of the nerve in the test. A de-embedding technique to build the equivalent transformer circuit model for the ICIM circuit is also presented. A batteryless PRF stimulator with ICIM circuit demonstrated good accuracy for the acute measurement of DRG impedance both in situ and in vivo. Besides, an in vivo animal experiment was conducted to show that the effectiveness of pulsed radiofrequency (PRF) stimulation in relieving pain gradually declined as the impedance of the stimulated nerve increased. The experiment also revealed that the excitation voltage for measuring impedance below 25 mV can prevent the excitation of a nonlinear response of DRG.

Improved de-embedding technique for polysilicon resistor modelling

In this article, accurate de-embedding technique based on transmission line theory is presented and applied to on-wafer polysilicon resistors fabricated in 130-nm SiGe technologies. Compared with the conventional de-embedding methods, not only the top metal layer, but also the under-layer metal parasitics are removed from the on-wafer passives. A systematic method relying exclusively on embedded S-parameters is used for the direct extraction of device circuit elements. This extracted method is characterised by its simplicity and ease of implementation. The proposed de-embedding technique and extraction approach are validated by polysilicon resistors with occupying areas of 20 × 2 µm2. Good agreement between the measured and modelled data is obtained from 100 MHz up to 20.1 GHz.

A de-embedding technique for metallic nanowires in microwave characterization

The application of metallic nanowires as transmission lines at microwave frequencies has attracted interest of the nanoelectronics community in recent years. The size reduction of wires down to nano-scale inevitably introduces more challenges not only in the fabrication but in the characterization techniques. The aim of this work is to build a reliable framework to characterize a single metallic nanowire in the millimeter wave range by means of a tailored-designed coplanar waveguide platform. We conduct a comprehensive analysis on the characteristic impedances and the propagation constants of nano-scale aluminum metallic wires in relation to the change of line dimension as a function of frequency from 1 to 100GHz. A method to subtract the effect of pads and contact impedance from the measurement based on an equivalent circuit model and a cascade-based de-embedding theory is employed. We propose a quasi-TEM equivalent circuit model in the analysis to predict the measured frequency-dependent transmission line parameters. A comparison between simulated and measured result will be presented.

A New Millimeter-Wave Fixture Deembedding Method Based on Generalized Cascade Network Model

In this letter, a universal cascade-based deembedding technique was presented for on-wafer characterization of the RF CMOS device. As compared with existing deembedding approaches, it is developed based on unique combinations of two THRU structures that enable efficient deembedding of fixture parasitics without any inaccurate lumped approximation or requirement of known standards. The proposed deembedding technique is validated on 0.13- μm CMOS devices and has been proven to be more accurate than existing lumped and cascade-based deembedding techniques. As a result, it gives deeper physical prediction on transistor gate capacitances and transconductance. Therefore, it is highly suitable to be applied for device characterization at millimeter-wave frequencies.

One-Port De-Embedding Technique for the Quasi-Optical Characterization of Integrated Components

We describe a one-port de-embedding technique suitable for the quasi-optical characterization of terahertz integrated components at frequencies beyond the operational range of most vector network analyzers. This technique is also suitable when the manufacturing of precision terminations to sufficiently fine tolerances for the application of a TRL de-embedding technique is not possible. The technique is based on vector reflection measurements of a series of easily realizable test pieces. A theoretical analysis is presented for the precision of the technique when implemented using a quasi-optical null-balanced bridge reflectometer. The analysis takes into account quantization effects in the linear and angular encoders associated with the balancing procedure, as well as source power and detector noise equivalent power. The precision in measuring waveguide characteristic impedance and attenuation using this de-embedding technique is further analyzed after taking into account changes in the power coupled due to axial, rotational, and lateral alignment errors between the device under test and the instruments' test port. The analysis is based on the propagation of errors after assuming imperfect coupling of two fundamental Gaussian beams. The required precision in repositioning the samples at the instruments' test-port is discussed. Quasi-optical measurements using the de-embedding process for a WR-8 adjustable precision short at 125 GHz are presented. The de-embedding methodology may be extended to allow the determination of S-parameters of arbitrary two-port junctions. The measurement technique proposed should prove most useful above 325 GHz where there is a lack of measurement standards.

High efficiency GaN current‐mode class‐D amplifier at 2.6 GHz using pure differential transmission line filters

In class-D operation the impedances of the output network at each harmonic frequency at the intrinsic terminals of the transistors are of main importance. This reported work demonstrates a new concept using pure differential transmission line filters for the matching of these impedances. Furthermore, de-embedding techniques are used to compensate the impedance transforming characteristics of the package parasitics. A current-mode class-D (CMCD) amplifier with a power-added efficiency (PAE) of 62% and a corresponding output power of 29.5 W at 2.6 GHz has been demonstrated. To the authors' knowledge, these are the highest reported values of the PAE as well as the output power at this frequency for a CMCD.

Through-Silicon-Via Characterization and Modeling Using a Novel One-Port De-Embedding Technique

SUMMARY In this paper, a novel and simple one-port de-embedding technique has been applied to through-silicon-via (TSV) characterization and modeling. This method utilized pad, via, and line structures to extract the equivalent circuit model of TSV. The main advantage of this deembedding method is that it can reduce the chip area to fabricate test element groups (TEGs) for measurements while keeping S-parameter measurement accuracies. We also analyzed the electrical characteristics of substrate coupling and TSV equivalent impedance. Our results shows good agreements between measurement data and the equivalent circuit model up to 20 GHz.

Limitations of On-Wafer Calibration and De-Embedding Methods in the Sub-THz Range

This paper investigates frequency limitations of calibration and de-embedding techniques for S parameter measurements. First, the TRL calibration methods are analysed and the error due to the probe movement when measuring the different line lengths is quantified, next the coupling between the probe-heads and the wafer surface is investigated and finally an upper frequency validity limit for the standard Open-Short de-embedding method is given. The measured results have been confirmed thanks to the use of an electro-magnetic simulator.

Nonlinear embedding and de-embedding techniques for large-signal fet measurements

The manuscript presents a comparison between two nonlinear procedures oriented to the investigation of the intrinsic I/V dynamic characteristics at a transistor's current-generator plane. These approaches, without the need of modeling device trapping and thermal effects, allow to obtain information at the current-generator reference plane that is more strictly linked to the device performance in terms of output power and efficiency. Experiments carried out on a 800-μm GaN HEMT are reported. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2835–2838, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27169

In Situ Silicon-Integrated Tuner for Automated On-Wafer MMW Noise Parameters Extraction Using Multi-Impedance Method for Transistor Characterization

In this paper, the design and use of an in situ tuner (IST) aiming On-Wafer multi-impedance method are presented. The conventional method using Off-Wafer tuner is limited by the frequency range and has high losses between this external tuner and the device under test (DUT). Here, the IST is placed near the DUT to achieve higher |Γ| and to cancel losses between the impedance generator and the device. The architecture of the tuner is based on variable lumped R and C elements fulfilled with cold-field-effect transistor and varactors controlled through biasing and associated to coplanar transmission line for phase shifting. Detailed and dedicated noise de-embedding technique is described to extract the four noise ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NF</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> , Γ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">opt</sub> ) parameters of 65-nm metal-oxide-semiconductor field-effect silicon transistors through the use of this in situ multi-impedance method. The 75-110 GHz noise test bench using cold-noise source method and the noise measurement are described showing transistor capabilities at MMW.

A Cascade-Parallel Based Noise De-Embedding Technique for RF Modeling of CMOS Device

In this letter, a unique cascade-parallel based noise de-embedding technique is presented for on-wafer device characterization and modeling. It utilizes two fully shielded THRU line structures and one OPEN structure that enable simultaneously de-embedding of series contact resistance, forward coupling and distributed parasitics of interconnect. Thus, it is more suitable for RF/millimeter wave noise characterization of lossy CMOS devices as compared to conventional lumped and cascade based de-embedding techniques. The proposed noise de-embedding technique is verified on both zero length THRU and OPEN devices. It demonstrates a better high frequency de-embedding performance than existing cascade based techniques by showing 1 dB improvement in predicted NFmin of 0.13 μm CMOS devices at 60 GHz. This is consistent with the further validation result on the de-embedded gain performance of the transistor.