DCT Processing Research Articles

Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation

A scheme often used for error tolerance of arithmetic circuits is the so-called Reduced Precision Redundancy (RPR). Rather than replicating multiple times the entire module, RPR uses reduced precision (inexact) copies to significantly reduce the redundancy overhead, while still being able to correct the largest errors. This paper focuses on the low-power operation for RPR; a new scheme is proposed. At circuit level, power gating is initially utilized in the arithmetic modules to power off one of the modules (i.e., the exact module) when the inexact modules’ error is smaller than the threshold. The proposed design is applicable to (unsigned integer) addition, multiplication, and MAC (multiply and add) by proposing RPR implementations that reduce the power consumption with a limited impact on its error correction capability. The proposed schemes have been implemented and tested for various applications (image and DCT processing). The results show that they can significantly reduce power consumption; moreover, the simulation results show that the Mean Square Error (MSE) at the proposed schemes’ output is low.

A Novel Approach of Watermarking for Multiple Images with DWT-DCT

A novel approach is discussed, to embed the multiple images (more than one image) with single cover image. More than one image coefficients are can be effectively embedded into cover image coefficients. The 3 images (cover image, 2 watermark images) are transformed into wavelet coefficients. One of the coefficients of watermark images LLw1 and LLw2 and cover image LLc and HHc are follows DCT and embedding process respectively. The resultant cover image hiding multiple watermark images respectively. The quantitative and qualitative analysis is discussed with Normalized Correlation (NC), Mean square error (MSE) and Peak Signal to noise ratio (PSNR).

Image Copy Detection Based on DCT Ordinal and Block Median

As for highly repetitive image of Internet, a new image algorithm combined with DCT and block median method is designed. As there is a certain correlation between low-frequency coefficient of DCT and image scaling, the sequence vector of DCT coefficients is introduced with block median method to make up the defect of DCT processing for multi-channel image supplied. Through the combination of DCT and block median method, the recall and precision of new algorithm is over 95%. New algorithm works well in image scaling, resists well against watermarking attack and is able to detect the copy of target image fast and accurately from a large scale image datasets.

Method for compressing audio signal using wavelet packet transform and apparatus thereof

An audio compression method using wavelet packet transform (WPT) in MPEG1 layer 3 (hereinafter referred to as “MP3”) and a system thereof are provided. The method comprises calculating perceptual energy by analyzing audio samples which are input based on a psychoacoustic model; according to comparison of the level of the calculated perceptual energy with a threshold, selectively determining a modified DCT (MDCT) processing window and a wavelet packet transform (WPT) processing window; by processing audio samples corresponding to the scopes of the determined windows in the MDCT and WPT, converting the audio samples into data on frequency domains; and quantizing the processed data on the frequency domains according to the number of assigned bits.

Polyphase Downsampling Based Multiple Description Coding Applied to H.264 Video Coding

This paper presents a video coding method that improves error resilient functionality of H.264 with good coding efficiency. The method is based on PD (polyphase downsampling) multiple description coding. The only changes to H.264 are inserting PD before the DCT process and having new data partitioning NAL units. A coded slice is sent on 3 data partitioning NAL units. A header NAL unit contains motion vectors and block modes. Each of the other two NAL units contains a description generated by PD multiple description coding. The experimental results on all 9 of the test sequences of JVT SVC show that the proposed method gives 0.5 to 5 dB enhancement over the existing H.264 FMO checker board mode with motion vector based error-concealment.

Image size conversion on DCT‐compressed data

AbstractThe authors propose a method for converting the image size of DCT‐compressed coded data. This method converts the image size using the DCT coefficients as is, without decoding the compressed data (inverse DCT processing). Compared to conventional methods in which scaling is performed in the image space, image quality is equal or superior, and the calculation burden is reduced to one‐half to one‐third. In addition, the order of the DCT for the original compressed data is preserved, and the image can be decoded using common inverse DCT processing even after size conversion. This is a feature not found in conventional scaling methods using DCT coefficients. The authors' method is viable for resolution scalable coding in instances in which data compressed using JPEG or other fixed order DCTs must be compatible and be processed at high speeds. © 2003 Wiley Periodicals, Inc. Syst Comp Jpn, 34(6): 100–109, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.1209

Region support DCT (RS-DCT) for coding of arbitrarily shaped texture

Object-based coding is a promising technique for next-generation coding. Arbitrarily shaped texture coding is the key technique for object-based coding. This paper proposes a new technique, called region support for arbitrarily shaped texture coding. The method is based on conventional 2D DCT, and has a special feature that the decoding process is achieved by a conventional DCT process. The proposed technique outperforms other techniques and involves low complexity in the decoder.

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

The two-dimensional discrete cosine transform (2D DCT) has been widely recognized as a key processing unit for image data compression/decompression. In this paper, the implementation of a 200 MHz 13.3 mm/sup 2/ 8/spl times/8 2-D DCT macrocell capable of HDTV rates, based on a direct realization of the DCT, and using distributed arithmetic is presented. The macrocell, fabricated using 0.8 /spl mu/m base-rule CMOS technology and 0.5 /spl mu/m MOSFET's, performs the DCT processing with 1 sample-(pixel)-per-clock throughput. The fast speed and small area are achieved by a novel sense-amplifying pipeline flip-flop (SA-F/F) circuit technique in combination with nMOS differential logic. The SA-F/F, a class of delay flip-flops, can be used as a differential synchronous sense-amplifier, and can amplify dual-rail inputs with swings lower than 100 mV. A 1.6 ns 20 bit carry skip adder used in the DCT macrocell, which was designed by the same scheme, is also described. The adder is 50% faster and 30% smaller than a conventional CMOS carry look ahead adder, which reduces the macrocell size by 15% compared to a conventional CMOS implementation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

VLSI implementation of two-dimensional DCT processor in real time for video codec

A new VLSI circuit for computing the two-dimensional discrete cosine transform (2D-DCT) using the Philips fast computational algorithm for a video codec in real time has been designed and tested using 1- mu m CMOS standard cell technology. This processor requires a minimum number of arithmetic components and satisfies the CCITT standards using a minimum possible number of bits for cosine coefficients and internal word length compared to other architectures. The architecture is so flexible that it can be used for inverse DCT processing just by changing the control signals. The architecture works in real time at a 32-MHz rate. The processor can be used for still picture and motion video compression. Due to its high-speed processing capability it can be used in video codecs at different bit rates. >