Abstract
A scheme often used for error tolerance of arithmetic circuits is the so-called Reduced Precision Redundancy (RPR). Rather than replicating multiple times the entire module, RPR uses reduced precision (inexact) copies to significantly reduce the redundancy overhead, while still being able to correct the largest errors. This paper focuses on the low-power operation for RPR; a new scheme is proposed. At circuit level, power gating is initially utilized in the arithmetic modules to power off one of the modules (i.e., the exact module) when the inexact modules’ error is smaller than the threshold. The proposed design is applicable to (unsigned integer) addition, multiplication, and MAC (multiply and add) by proposing RPR implementations that reduce the power consumption with a limited impact on its error correction capability. The proposed schemes have been implemented and tested for various applications (image and DCT processing). The results show that they can significantly reduce power consumption; moreover, the simulation results show that the Mean Square Error (MSE) at the proposed schemes’ output is low.
Highlights
T HE development of ever smaller devices brings promise for further improvement in the performance of future integrated circuits, yet it leads to several new technical challenges, including the need for nanoarchitectures that reduce the uncertainty inherent to computation and communication at such small scales [1]
There are many techniques to protect a digital circuit against so-called soft errors; one of the most common schemes is the use of replication, so either by Dual Modular Redundancy (DMR) to detect errors or Triple
This paper has presented novel schemes for Approximate Reduced Precision Redundancy (ARPR) as applicable to commonly used operations, such as multiplication, addition, and MAC in an unsigned integer format
Summary
Ke Chen, Member, IEEE, Weiqiang Liu, Senior Member, IEEE, Ahmed Louri, Fellow, IEEE, and Fabrizio Lombardi, Fellow, IEEE (A scheme often used for error tolerance of arithmetic circuits is the so-called Reduced Precision Redundancy (RPR). Rather than replicating multiple times the entire module, RPR uses reduced precision (inexact) copies to significantly reduce the redundancy overhead, while still being able to correct the largest errors. This paper focuses on the low-power operation for RPR; a new scheme is proposed. The proposed design is applicable to (unsigned integer) addition, multiplication, and MAC (multiply and add) by proposing RPR implementations that reduce the power consumption with a limited impact on its error correction capability. The results show that they can significantly reduce power consumption; the simulation results show that the Mean Square Error (MSE) at the proposed schemes’ output is low.)
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