Abstract
This work analyzes the performance of the reduced precision redundancy (RPR) error mitigation technique using the fast Fourier transform (FFT) as a case study. To this purpose, several configurations of an FFT IP design were implemented in field-programmable gate array (FPGA) using reduced precision triple modular redundancy (RP-TMR) and tested under proton irradiation and fault injection. The cross section, the sensitivity to common-mode failures (CMFs), and the signal-to-noise ratio of these configurations were evaluated. The results of the radiation experiments and fault injection campaigns are in agreement and show that the RP-TMR technique may be used as an alternative to triple modular redundancy (TMR) if small errors can be tolerated, as it has a good performance in terms of error correction capabilities, area usage, and sensitivity to critical errors.
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