DC Servo Loop Research Articles

A low noise instrument amplifier in 40 nm CMOS with positive feedback loop and DC servo loop for neural signal acquisition

A low noise instrument amplifier in 40 nm CMOS with positive feedback loop and DC servo loop for neural signal acquisition

A chopper instrumentation amplifier with discrete-time compensation based on current generation unit to eliminate electrode DC offset

A capacitively-coupled chopper instrumentation amplifier (CCIA) for bio-potential signals acquisition is proposed in this paper. A novel discrete-time compensation scheme based on the current generation unit is adopted to suppress the DC offset caused by the sampling electrode. Different with the traditional analog DC servo loop (DSL) used in previous works, the circuit based on this scheme is more straightforward and consumes less power. Moreover, it can suppress a larger electrode DC offset in a short time. This work is designed in a standard 180 nm CMOS process. The CCIA operates from a 1.8 V supply, from which it draws a total current of 0.72 μA. The simulation result shows that the signal bandwidth of the proposed CCIA is 1.2 – 500 Hz and the mid-band gain is about 31.49 dB. In the frequency band of 1 – 500 Hz, the input-referred noise of the circuit is 2.01 μVrms. Inputting a single-tone sine wave with an amplitude of 14.1 mV at the frequency of 56.152 Hz, the total harmonic distortion (THD) of the CCIA’s output is −51.38 dB. This circuit can suppress a large electrode DC offset within a few milliseconds, and the maximum electrode DC offset that can be tolerated up to 130 mV.

An instrumentation amplifier with series switch pseudo resistor DC-servo loop realizing 0.16-Hz high-pass corner

This paper presents an instrumentation amplifier for electrocardiogram (ECG) signal recording. A DC servo loop (DSL) based on a series-switch pseudo resistor (S2PR ) is utilized to suppress the effect of the unavoidable electrode DC offset effectively. The two-step pulse generation circuit realizes two sets of pulse signals with shallow duty cycles, and the pulse signals drive the path switches and virtual switches in the S2PR, respectively. Virtual switches reduce the channel charge injection effect, and finally, a great equivalent resistance with high linearity is realized. The continuous DSL realized based on S2PR can suppress the electrode DC offset of ±180 mV. At the same time, the active area of the DSL is significantly reduced. The proposed instrumentation amplifier is realized in a standard 0.18-μm CMOS process. Simulation results show the DSL designed with a 1.8-V supply introduces a 0.16-Hz high-pass corner. The power consumption of the S2PR-DSL is 92.7 μW. The gain of the instrumentation amplifier is 39.8 dB, and the input-referred noise at the TT corner is 1.78 μVrms over a bandwidth of 0.5 Hz to 150 Hz. The input impedance of the instrumentation amplifier is 772.2 MΩ, when the input signal frequency is 50 Hz, and the total harmonic distortion (THD) of a 10-mVpp input sinusoidal signal at 9.033 Hz is −61.6 dB.

A LFP/AP Mode Reconfigurable Analog Front-End Combining an Electrical EEEG-iEEG Model for the Closed-Loop VNS.

This article presents a local field potential (LFP)/action potential (AP) mode reconfigurable analog front-end (AFE) dedicated for the closed-loop vagus nerve stimulator (VNS). It combines an inverse electrical model of the intracranial electroencephalogram (iEEG) conducting in the brain tissues and been recorded at scalp as the extended electroencephalogram (EEEG). The AFE contains a LFP/AP mode reconfigurable EEEG preamplifier, a tunable integrator to compensate the effect of either the recording electrodes or head tissues, and an adder. The LFP/AP mode reconfigurable EEEG preamplifier consists of a tunable chopper-stabilized amplifier (CSA) and a 2nd-order tunable low pass filter (LPF). For better separation of LFP and AP signals, a high-order DC servo loop (DSL) characterized as a 2nd-order DSL in parallel with a 1st-order DSL is exploited in the tunable CSA to achieve a tunable high-pass frequency with a stopband attenuation slope (SAS) of +40 dB/dec. In addition, the tunable LPF can obtain a tunable low-pass frequency with a SAS of -40 dB/dec and provide additional 20 dB gain for AP signals. Fabricated in a SMIC 180 nm CMOS technology, and in the LFP band (0.5 Hz-200 Hz) and AP band (300 Hz-5 kHz), the measured mid-band gains of the LFP/AP mode reconfigurable EEEG preamplifier are 39.6 dB and 59.5 dB, the input-referred noises (IRNs) are 2.2 μVrms and 6.3 μVrms, the DC/in-band input impedances are 1.27/1.26 GΩ and 0.3/0.22 GΩ, respectively. The power consumption per channel AFE is 6.3 μW, and the die area is 1.4 mm × 0.25 mm.

A Capacitive-Feedback Amplifier with 0.1% THD and 1.18 μVrms Noise for ECG Recording

This paper presents an amplifier with low noise, high gain, low power consumption, and high linearity for electrocardiogram (ECG) recording. The core of this design is a chopper-stabilized capacitive-feedback operational transconductance amplifier (OTA). The proposed OTA has a two-stage structure, with the first stage using a combination of current reuse and cascode techniques to obtain a large gain at low power and the second stage operating in Class A state for better linearity. The amplifier additionally uses a DC servo loop (DSL) to improve the rejection of DC offsets. The amplifier is implemented in a standard 0.13 μm CMOS process, consuming 1.647 μA current from the supply voltage of 1.5 V and occupying an area of 0.97 mm2. The amplifier has a 0.5 Hz to 6.1 kHz bandwidth and 59.7 dB gain while having no less than a 65 dB common-mode rejection ratio (CMRR). The amplifier’s total harmonic distortion (THD) is less than 0.1% at 800 mVpp output. The amplifier can provide a noise level of 1.18 μVrms in the 0.5 Hz to 500 Hz bandwidth that the ECG signal is interested in and has 3.38 μVrms input-referred noise (IRN) over the entire bandwidth, so its noise efficiency factor (NEF) is 2.13.

A Hybrid Magnetic Current Sensor With a Dual Differential DC Servo Loop

A Hybrid Magnetic Current Sensor With a Dual Differential DC Servo Loop

A 0.26 [formula omitted]Vrms instrumentation amplifier based on discrete-time DC servo loop with successive-approximation-compensation technique and Chopper DAC Array

A low-noise instrumentation amplifier for bio-signal recording is proposed in this paper. One of the significant disturbances, electrode DC offset, is suppressed using the proposed successive-approximation-compensation (SAC) circuit based on a discrete-time DC servo loop with Chopper DAC Array. Firstly, the DC offset at the output is quantified using the SAR quantizer. Next, the digital code produced by the SAR quantizer is used to control the chopper DAC array. Finally, a suitable compensation voltage is generated and used directly to correct the electrode DC offset at the input of the chopper amplifier. By using the proposed compensation technique, the first-stage chopper amplifier’s quiescent operating state is unaffected. When a 50-mV DC offset voltage exists at the differential input, the SAC circuit can compensate the DC offset voltage close to zero in a relatively short time. At the same time, there are fewer capacitors, which significantly decrease the area consumption. The proposed instrumentation amplifier is implemented in a standard 0.18μm CMOS process. The experiment results show that over a bandwidth from 0.1 Hz to 100 Hz, an input referred noise of 0.26 μVrms at the TT corner has been attained. The total power consumption is about 13.72 μW at the supply voltage of 1.8 V. The gain of the instrumentation amplifier is about 39.15 dB and its Noise Efficiency Factor (NEF) is 2.76.

A Low-Noise and Low-Power Multi-Channel ECG AFE Based on Orthogonal Current-Reuse Amplifier

This paper proposes a low-noise and low-power current-reuse analog front-end (AFE) for multi-channel electrocardiography (ECG) acquisition. A new low-power orthogonal recombination method is proposed in the four-channel current-reuse amplifier, which reduces the recombination current by half and cuts down the power supply voltage while ensuring the crosstalk suppression capability, resulting in a lower average channel power consumption. A four-order current-cancellation subthreshold-source-follower low-pass filter (CS-LPF) is proposed in this paper, which realizes the reduction of the chip area and power consumption by cross-coupling current cancellation technology. In addition, the input impedance boosting circuit, DC servo loop (DSL), and successive approximation register analog-to-digital converter (SAR-ADC) are designed in the proposed AFE, and it can record and quantify ECG signals. The presented AFE was implemented in a 65nm CMOS process, and the core area is 1.42mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.85mm. The measured results show that the proposed AFE has a variable gain of 40.5-56dB. The fully differential low-pass filter with a power consumption of only 4.8nW achieves 50% capacitance reduction. The average power consumption per channel of the proposed AFE is only 2.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W, and the power efficiency factor (PEF) and noise efficiency factor (NEF) are 3.93 and 1.81 respectively.

A Micropower Chopper CBIA with DSL-Embedded Input Stage with 0.4 V EO Tolerance for Dry-Electrode Biopotential Recording.

A chopper instrumentation amplifier (IA) dedicated for bio-potential acquisition usually requires a linearized input stage for large electrode offset voltage accommodation. This linearization leads to excessive power consumption when sufficiently low input-referred noise (IRN) is required. We present a current-balance IA (CBIA) without the need for the input stage linearization. It uses two transistors to operate as an input transconductance stage and a dc-servo loop (DSL) at the same time. An off-chip capacitor completes the DSL by ac coupling the source terminals of the input transistors via chopping switches realizing a sub-Hz high-pass cutoff frequency for dc rejection. Fabricated in a 0.35-μm CMOS process, the proposed CBIA occupies 0.41 mm2 and consumes 1.19 μW from a 3 V dc supply. Measurements show that the IA achieves an input-referred noise of 0.91 μVrms over 100 Hz bandwidth. This corresponds to a noise efficiency factor of 2.22. Typical CMRR of 102.1 dB is achieved for zero offset and degraded to 85.9 dB when a ±0.3 V input offset was applied. Gain variation of 0.5% is maintained within the range of ±0.4V input offset. The resulting performance meets well with the requirement for ECG and EEG recording using dry electrodes. A demonstration for the use of the proposed IA on a human subject is also provided.

A chopper amplifier with a low duty‐cycle sub‐sampling in the switched‐capacitor integrator for noise reduction

AbstractThis letter presents a low‐noise implementation of the switched‐capacitor (SC) DC servo loop (DSL) in the capacitively coupled chopper instrumentation amplifier (CCIA). The noise of the SC integrator in SC DSL is first analyzed, then a low duty‐cycle subsampling and unbalanced capacitor ratio are proposed to reduce the noise. Fabricated in a 65‐nm complementary metal‐oxide semiconductor (CMOS) process, the CCIA achieves 2.5 μVrms input‐referred noise, integrated from 0.5 to 250 Hz, and 110‐mV electrode‐DC offset (EDO) cancellation range. Besides, the calculated noise of the SC integrator well matches the measured, which proves the noise analysis. Compared with prior designs adopting similar SC integrators, this work reduces the noise level by 2× and increases the cancellation range by 2×.

A 672-nW, 670-nVrms ECG Acquisition AFE With Noise-Tolerant Heartbeat Detector

This paper presents an electrocardiogram acquisition analog front-end (AFE) with a noise tolerant heartbeat (HB) detector. Source degradation and transconductance bootstrap techniques are incorporated into the AFE to reduce the 1/f noise of the amplifier. Furthermore, the chopper modulation, DC-servo loop (DSL) and pre-charge technology are combined to reduce interference from the environment. A mixed-signal implementation of HB detector with the symmetric-comparison loop is proposed to reduce the power consumption and area, which also suppresses motion artifact interference by adaptive thresholds. Implemented in 0.18 μm CMOS process, the circuit only occupies an area of 0.122 mm2 and consumes 0.62 μW at a 1.2-V supply, of which AFE and HB detector consume 507 nW and 110 nW, respectively. Simulation results show that the gain and the CMRR of AFE range from 30-45 dB and 65-105 dB, respectively. The input-referred noise is 670 nVrms with a mid-band gain of 42 dB and a bandwidth ranging from 0.5 Hz to 1 kHz.

NeuralTree: A 256-Channel 0.227-μJ/Class Versatile Neural Activity Classification and Closed-Loop Neuromodulation SoC.

Closed-loop neural interfaces with on-chip machine learning can detect and suppress disease symptoms in neurological disorders or restore lost functions in paralyzed patients. While high-density neural recording can provide rich neural activity information for accurate disease-state detection, existing systems have low channel counts and poor scalability, which could limit their therapeutic efficacy. This work presents a highly scalable and versatile closed-loop neural interface SoC that can overcome these limitations. A 256-channel time-division multiplexed (TDM) front-end with a two-step fast-settling mixed-signal DC servo loop (DSL) is proposed to record high-spatial-resolution neural activity and perform channel-selective brain-state inference. A tree-structured neural network (NeuralTree) classification processor extracts a rich set of neural biomarkers in a patient- and disease-specific manner. Trained with an energy-aware learning algorithm, the NeuralTree classifier detects the symptoms of underlying disorders (e.g., epilepsy and movement disorders) at an optimal energy-accuracy trade-off. A 16-channel high-voltage (HV) compliant neurostimulator closes the therapeutic loop by delivering charge-balanced biphasic current pulses to the brain. The proposed SoC was fabricated in 65nm CMOS and achieved a 0.227μJ/class energy efficiency in a compact area of 0.014mm2/channel. The SoC was extensively verified on human electroencephalography (EEG) and intracranial EEG (iEEG) epilepsy datasets, obtaining 95.6%/94% sensitivity and 96.8%/96.9% specificity, respectively. In-vivo neural recordings using soft μECoG arrays and multi-domain biomarker extraction were further performed on a rat model of epilepsy. In addition, for the first time in literature, on-chip classification of rest-state tremor in Parkinson's disease (PD) from human local field potentials (LFPs) was demonstrated.

A Direct Digitizing Chopped Neural Recorder Using a Body-Induced Offset Based DC Servo Loop.

This article presents a direct digitizing neural recorder that uses a body-induced offset based DC servo loop to cancel electrode offset (EDO) on-chip. The bulk of the input pair is used to create an offset, counteracting the EDO. The architecture does not require AC coupling capacitors which enables the use of chopping without impedance boosting while maintaining a large input impedance of 238 M Ω over the whole 10 kHz bandwidth. Implemented in a 180 nm HV-CMOS process, the prototype occupies a silicon area of only 0.02 mm2 while consuming 12.8 μW and achieving 1.82 μV[Formula: see text] of input-referred noise in the local field potential (LFP) band and a NEF of 5.75.

Neckband-Based Continuous Blood Pressure Monitoring Device With Offset-Tolerant ROIC

This study presents a wearable neckband device for continuous cuffless blood pressure (BP) monitoring, where reliable neck-based BP measurement is achieved by utilizing the electrocardiogram (ECG) and impedance plethysmogram (IPG). Optimal composition and position of sensing electrodes around the neck were decided with consideration for physiological characteristics of the human body, and the core parameter of IPG magnitude was experimentally selected to improve the BP estimation accuracy. For its small-featured noises-tolerant detection capability, a customized readout integrated circuit (ROIC) was developed, which includes two kinds of analog front-ends (AFEs) for biopotential and bio-impedance. Both AFEs are proposed to include an attenuator-assisted hybrid DC-servo loop (DSL) structure, achieving precise pulse transit time (PTT) calculation by lowering the high-pass filtering cutoff frequency and also stable signal acquisition by widening the offset-cancellation range. Real-time PTT monitoring and BP estimation are wirelessly conducted, and its continuous operation time with 350-mAh battery capacity is longer than 5 hours. Efficacy of the proposed neckband BP device was evaluated for 8 healthy subjects under the physical stress condition, where the mean correlation coefficient and the standard deviation were achieved as 0.8508 and 4.17mmHg respectively.

A Bio-IA With Fast Recovery and Constant Bandwidth for Wearable Bio-Sensors

This paper proposes a bio-signal instrumentation amplifier (Bio-IA) with fast recovery and constant bandwidth for wearable bio-sensors. To shorten the offset calibration time of the Bio-IA and reduce the loss of bio-signal in the calibration process, a digital-controlled DC servo loop (DCDSL) with fast recovery is designed, which achieves a larger offset calibration range and a faster calibration speed. The proposed programmable gain amplifier (PGA) with constant bandwidth uses dual-biased pseudo-resistor (PR) to stabilize the passband width under different gains, effectively preventing the loss of low-frequency signals. Besides, this paper analyzes the noise of the DCDSL and the noise of dual-biased PR for the first time. The presented Bio-IA was implemented in a 0.18- μm CMOS process, occupying a core area of 849 μm×451 μm. The measured results show that the Bio-IA can calibrate a DC offset of ±511 mV, and the response time is less than 70 ms when the offset polarity changes suddenly. When the gain of the Bio-IA varies from 26 to 40 dB, its passband width remains constant, and the high-pass and low-pass cut-off frequencies are 0.4 Hz and 200 Hz, respectively. The input-referred noise over the range of 0.1-200 Hz is 0.72 μVrms. The proposed Bio-IA consumes 5.5 μW from 1.2 V supply voltage.

A Closed-Loop Neuromodulation Chipset With 2-Level Classification Achieving 1.5-Vpp CM Interference Tolerance, 35-dB Stimulation Artifact Rejection in 0.5ms and 97.8%-Sensitivity Seizure Detection.

This work presents an 8-channel closed-loop neuromodulation chipset with 2-level seizure classification. The power-consuming fine classifier is only enabled when the coarse classifier in the frontend chip judges the patient's status as "suspected seizure". This scheme can reduce the overall power consumption extensively since seizure usually occurs with very low possibility. In the capacitive-coupled instrument amplifier (CCIA) of the front-end IC, a feedback based common-mode (CM) cancellation circuit is proposed to suppress large-scale CM interferences and the stimulation artifacts are suppressed by a mixed-signal loop with fast response. An auto-zero based pre- charge path is adopted to boost the input impedance, while the electrode DC offset is canceled by a DC servo loop with very-large and accurate time constant. The 2.32-mm2 front-end chip and 3.51-mm2 DSP chip implemented in 0.18 μm CMOS are applied in a deep-brain stimulation (DBS) neuromodulator. Measurement results show that the CCIA can suppress 1.5-Vpp CM interference, and achieve an accurate high-pass corner frequency as low as 0.1 Hz and an input impedance greater than 2.2 GΩ. The overall classifier achieves 97.8% sensitivity and consumes only 1.16-μW average power for the CHB-MIT database test. The chipset has been verified by in vivo measurement, showing that the stimulation artifact can be suppressed by 35 dB within 0.5 ms.

Low-voltage high-linear Gm-transimpedance instrumentation amplifier with robust feedforward biasing against PVT variations

A new gm-transimpedance instrumentation amplifier (GTIA) is introduced that enables precision signal acquisition with low-power operation. The GTIA architecture employs an input current-mode gm stage to achieve high-linearity and low-noise specs simultaneously. For biomedical applications, a bootstrapped AC coupling scheme is devised which maintains rail-to-rail electrode offset tolerance and gigaohms level input impedance. The amplifier gain is set by a single feedback resistor to over 80 dB with 2nd-order bandpass filter response. Also, an innovative feedforward biasing technique is proposed that yields robust operation along with adaption to different ranges of supply voltage. The circuit is implemented in 0.18 μm CMOS process and consumes 40 and only 1.12 μW of power at 1.2 and 0.8 V. Several simulations have been carried out to characterize the designed GTIA. Total input-referred noise equals 0.88 and 3.17 μVRMS within frequencies of 0.5–100 and 0.1–150 k Hz, respectively. Input offset voltage equals 2.6 μV regulated via the DC servo loop (DSL) circuit which does not degrade the noise performance. CMRR of the designed GTIA is up to 105 dB without sensitivity to variation of the feedback resistor and the THD is less than 0.015% for a 2 mVpp input signal.

A 0.52 μW, 38 nV/√Hz Chopper Amplifier With a Low-Noise DC Servo Loop, an Embedded Ripple Reduction Loop, and a Squeezed Inverter Stage

To realize an ultralow-power, low-noise amplifier for bio-potential recording, we investigate three design techniques. The first technique uses a noise-efficient squeezed inverter (SQI) stage biased at the supply of the $2{V} _{\mathrm{ DSAT}}$ saturation limit. The challenge of interfacing the SQI stage with such a low supply is addressed by proposing a new capacitively-coupled chopper instrumentation amplifier (CCIA) with a low-noise DC servo loop (L-DSL) and an embedded ripple reduction loop (E-RRL). The second technique is reducing the high noise contribution of the conventional DSL. The proposed L-DSL reduces the input-referred noise (IRN) by removing the charge dividing effect. The proposed E-RRL inserted inside the gain stage cancels the offset and achieves a ripple suppression without loading the output. The CCIA is implemented using a $0.18~\mu \text{m}$ CMOS process. The measured results show that the L-DSL successfully creates a sub-Hz high-pass corner needed to block the electrode offset. The E-RRL achieves a ripple suppression of 39 dB. The CCIA achieves 32 nV/ $\surd $ Hz noise density, which is slightly increased to 38 nV/ $\surd $ Hz when the L-DSL is enabled. The integrated noise over 800 Hz bandwidth is 0.9 and 1.1 $\mu \text{V}_{\mathrm{ rms}}$ without and with the L-DSL, respectively. The mid-band gain of 39.6 dB is achieved by consuming $0.52~{\mu }\text{W}$ . These results correspond to a favorable noise efficiency factor (NEF) of 2.1 and a power efficiency factor (PEF) of 1.2.

Design of a Low Noise Bio-Potential Recorder With High Tolerance to Power-Line Interference Under 0.8V Power Supply.

A bio-potential recorder working under 0.8V supply voltage with a tunable low-pass filter is proposed in this paper. The prototype is implemented in TSMC 180nm CMOS technology, featuring a power consumption of 2.27 μW, while preserving a high tolerance of power-line interference (PLI) up to 600m Vpp, a common-mode rejection ratio (CMRR) of higher than 100dB, a THD of -65.5dB, and a noise density of 50 nV/ √{Hz} by employing four new techniques, including 1) low noise chopper modulator, 2) feedback loop based common-mode cancellation loop (CMCL), 3) offset cancellation loop (OCL) with PMOS backgate control scheme, and 4) a very-lower transconductance (VLT) operational transconductance amplifier (OTA) using in the DC-servo-loop (DSL). The measured mid-band gain is 43.3dB with a high-pass cut-off frequency of 1.2Hz. The low-pass cut-off frequency can be configured from 650Hz to 7.5kHz. The measured input-referred integrated noise is 1.2 uVrms in the frequency band of 1-650Hz and 4.1 uVrms in the 1 Hz-7.5kHz frequency band, respectively, leading to a power efficiency factor (PEF) of 7.49 and 7.59.

A 2.6 GΩ, 1.4 μVrms current-reuse instrumentation amplifier for wearable electrocardiogram monitoring

This brief presents a high input impedance current-reuse instrumentation amplifier for wearable electrocardiogram monitoring. The IC has three main parts, namely, current-reuse amplifier, ripple reduction loop, and DC-servo loop. A current-reuse amplifier is introduced to realize multi-channel with one amplifier. A special chopper-stabilized technique is employed to eliminate the 1/f noise and boost the input impedance. A ripple-reduction loop is employed to suppress the ripple caused by the chopper modulator. Meanwhile, A DC-servo loop with chopper modulator is implemented to suppress the electrode offset. Fabricated in SMIC 180 nm CMOS process, the proposed instrumentation amplifier occupies an active area of 0.31 mm2, draws 6.6 μA from a 1.8 V supply voltage, and achieves an input impedance in the order of giga-ohms, input referred noise as low as 1.4 μVrms.