Design of a Low Noise Bio-Potential Recorder With High Tolerance to Power-Line Interference Under 0.8V Power Supply.

Deng Luo,Jiaxin Lei,Milin Zhang,Zhihua Wang

doi:10.1109/tbcas.2020.3038632

Abstract

A bio-potential recorder working under 0.8V supply voltage with a tunable low-pass filter is proposed in this paper. The prototype is implemented in TSMC 180nm CMOS technology, featuring a power consumption of 2.27 μW, while preserving a high tolerance of power-line interference (PLI) up to 600m Vpp, a common-mode rejection ratio (CMRR) of higher than 100dB, a THD of -65.5dB, and a noise density of 50 nV/ √{Hz} by employing four new techniques, including 1) low noise chopper modulator, 2) feedback loop based common-mode cancellation loop (CMCL), 3) offset cancellation loop (OCL) with PMOS backgate control scheme, and 4) a very-lower transconductance (VLT) operational transconductance amplifier (OTA) using in the DC-servo-loop (DSL). The measured mid-band gain is 43.3dB with a high-pass cut-off frequency of 1.2Hz. The low-pass cut-off frequency can be configured from 650Hz to 7.5kHz. The measured input-referred integrated noise is 1.2 uVrms in the frequency band of 1-650Hz and 4.1 uVrms in the 1 Hz-7.5kHz frequency band, respectively, leading to a power efficiency factor (PEF) of 7.49 and 7.59.

Highlights

A POWER efficient bio-potential recorder plays a critical role in a Brain-Machine-Interface (BMI) system [1]–[3]
This paper focuses on the design of the chopper amplifier
The proposed design was fabricated in TSMC 180 nm CMOS process with a silicon area of 0.25 mm 2

Summary

Introduction

A POWER efficient bio-potential recorder plays a critical role in a Brain-Machine-Interface (BMI) system [1]–[3]. Various methodologies have been proposed in literature aiming to the reduction of power consumption. The majority of those existing low power designs improved power consumption performance by reducing the current, but sacrificing the noise performance. In order to optimize the power efficiency factor (PEF), [8]–[10] proposed to reduce the supply voltage to sub-V, but leading to higher total harmonic distortion (THD). These circuits are susceptible to the common-mode interference (CMI), especially the power-line interference (PLI). The amplitude of the PLI can be as high as hundreds of millivolts at 50 Hz [11]

Methods

Results

Conclusion