A 0.52 μW, 38 nV/√Hz Chopper Amplifier With a Low-Noise DC Servo Loop, an Embedded Ripple Reduction Loop, and a Squeezed Inverter Stage

Abstract

To realize an ultralow-power, low-noise amplifier for bio-potential recording, we investigate three design techniques. The first technique uses a noise-efficient squeezed inverter (SQI) stage biased at the supply of the $2{V} _{\mathrm{ DSAT}}$ saturation limit. The challenge of interfacing the SQI stage with such a low supply is addressed by proposing a new capacitively-coupled chopper instrumentation amplifier (CCIA) with a low-noise DC servo loop (L-DSL) and an embedded ripple reduction loop (E-RRL). The second technique is reducing the high noise contribution of the conventional DSL. The proposed L-DSL reduces the input-referred noise (IRN) by removing the charge dividing effect. The proposed E-RRL inserted inside the gain stage cancels the offset and achieves a ripple suppression without loading the output. The CCIA is implemented using a $0.18~\mu \text{m}$ CMOS process. The measured results show that the L-DSL successfully creates a sub-Hz high-pass corner needed to block the electrode offset. The E-RRL achieves a ripple suppression of 39 dB. The CCIA achieves 32 nV/ $\surd $ Hz noise density, which is slightly increased to 38 nV/ $\surd $ Hz when the L-DSL is enabled. The integrated noise over 800 Hz bandwidth is 0.9 and 1.1 $\mu \text{V}_{\mathrm{ rms}}$ without and with the L-DSL, respectively. The mid-band gain of 39.6 dB is achieved by consuming $0.52~{\mu }\text{W}$ . These results correspond to a favorable noise efficiency factor (NEF) of 2.1 and a power efficiency factor (PEF) of 1.2.