DC Performance Research Articles

Hetero dielectric based dual material gate AlGaN channel MISHEMT for enhanced electrical characteristics

Herein, we report an AlGaN channel metal insulator semiconductor high electron mobility transistor (MISHEMT) in dual material gate (DMG) architecture with two different dielectrics as gate insulator for enhancing the DC performance of the device. The use of a high-k dielectric material as gate insulator below gate metal 1 and a low-k dielectric below gate metal 2 results in significant threshold voltage variation along the channel. This contributes to improved average carrier velocity which in turn results in better current drive. The proposed device exhibits a peak current of 162 mA/mm at zero gate bias, whereas, the DMG and single material gate (SMG) AlGaN channel HEMTs offer currents of 137 mA/mm and 125 mA/mm respectively. The peak transconductances are about 24.66 mS/mm, 23.68 mS/mm and 22.71 mS/mm respectively for the proposed device, DMG and SMG HEMTs. The proposed device reduces the OFF current by an order of 106 compared to that of DMG HEMT.

NPDC structure double-channel N-polar E-mode GaN HEMTs: Innovations in enhancing RF and DC performance and mitigating trap effects

—High-electron-mobility transistors (HEMTs) based on gallium nitride (GaN) are favored for their exceptional performance in high-power and high-frequency applications. However, developing dual-channel HEMTs presents challenges due to spontaneous polarization effects and design complexities. This study introduces a novel N-polar E-mode GaN HEMT with a dual-channel structure, featuring recessed drain-source regions and non-alloyed ohmic contacts. TCAD simulations provide theoretical insights and optimization strategies for these structures, focusing on the combination of N-polar GaN and ultra-wide bandgap AlN barrier layers. The optimized device demonstrates a threshold voltage of +1.08 V and a 45.9 % increase in current density. The N-polar double-channel HEMT (NPDC-HEMT) exhibited a 55.75 % improvement in peak transconductance, with Ft increasing from 13.3 GHz to 30.1 GHz and Fmax from 63.7 GHz to 65.9 GHz. Further enhancement was achieved in the T-gate variant (NPDC-T-HEMT), with Ft reaching 52.6 GHz and Fmax 94.4 GHz. The dual-channel design effectively mitigated short-channel effects and current collapse, demonstrating the potential for high-power RF applications.

TCAD‐enabled machine learning framework for DC and RF performance evaluation of InGaAs sub‐channel DG‐HEMTs

AbstractThis research presents a machine learning (ML)‐based model that determines the DC and RF characteristics of InGaAs sub‐channel double gate high electron mobility transistors (DG‐HEMTs) to optimize the device structure. We employ technology computer‐aided design (TCAD) simulations to analyze the DC and RF performance of InGaAs sub‐channel DG‐HEMTs, generating a range of datasets by varying the material composition, layer width, and thickness of different layers in the device structure. We then train and optimize support vector regression (SVR) models using 5‐fold cross‐validation, varying the kernel function and degree parameters, and achieve better performance with the radial basis function (RBF) kernel. The simulated results indicate that the ML model predicts physical parameters more effectively than experimental analysis, offering a compact modeling solution that requires fewer computing resources than traditional methods.

DC and AC Performance of InGaZnO Thin-Film Transistors on Flexible PEEK Substrate

DC and AC Performance of InGaZnO Thin-Film Transistors on Flexible PEEK Substrate

Improvement of DC Performance and RF Characteristics in GaN-Based HEMTs Using SiNx Stress-Engineering Technique.

In this work, the DC performance and RF characteristics of GaN-based high-electron-mobility transistors (HEMTs) using the SiNx stress-engineered technique were systematically investigated. It was observed that a significant reduction in the peak electric field and an increase in the effective barrier thickness in the devices with compressive SiNx passivation contributed to the suppression of Fowler-Nordheim (FN) tunneling. As a result, the gate leakage decreased by more than an order of magnitude, and the breakdown voltage (BV) increased from 44 V to 84 V. Moreover, benefiting from enhanced gate control capability, the devices with compressive stress SiNx passivation showed improved peak transconductance from 315 mS/mm to 366 mS/mm, along with a higher cutoff frequency (ft) and maximum oscillation frequency (fmax) of 21.15 GHz and 35.66 GHz, respectively. Due to its enhanced frequency performance and improved pinch-off characteristics, the power performance of the devices with compressive stress SiNx passivation was markedly superior to that of the devices with stress-free SiNx passivation. These results confirm the substantial potential of the SiNx stress-engineered technique for high-frequency and high-output power applications, which are crucial for future communication systems.

Innovative Spacer material integration in Tree-FETs for enhanced performance across Variable channel lengths

This work presents a novel three-channel Tree-FET optimized for superior DC and analog performance metrics. The device structure features nanosheets with a width (NSWD) of 9 nm, a thickness (NSTH) of 5 nm, and interbidge dimensions of 8 nm in height (IBHT) and 5 nm in width (IBWD). The Tree-FET demonstrates an exceptional on/off current ratio of 107 through meticulous engineering, significantly outperforming conventional FET configurations. Our comprehensive study explores the effects of different spacer materials, including HfO2, Al2O3, Si3N4, and SiO2, across varied channel lengths. The superior dielectric properties of HfO2 contribute to fine-tuning the device's characteristics, making it a standout choice for optimizing performance. Out of all HfO2 has been found to perform exceptionally well, offering the best combination of electrostatic control and minimized leakage currents. Because the Tree-FET has better electrostatic integrity and can keep working well with different spacer materials and channel lengths, it has much potential as a flexible and valuable part for next-generation semiconductor devices. The promising DC and analog metrics achieved through this novel design pave the way for developing more compact, high-performance electronic components.

Yield analysis of a BIPV façade prototype installation

Building integrated photovoltaics (BIPV) typically operate under different conditions compared to standard PV due to non-optimal orientations, poor ventilation, or additional losses in coloured modules. In this work, a test site for BIPV curtain wall façades was constructed at the Technical University of Denmark (DTU) and monitored for a full year. This data is used to analyze various performance aspects, including operating temperatures, power optimizer efficiencies, and DC performance ratios. In addition, parts of the system are modelled in SAM and results of this simulation are used to identify errors. In addition to this analysis, the underlying data set is published for researchers to use in model validation.

(Invited) Organic Permeable-Base Transistors: Physically Motivated Simplification of Device Structure for Modeling and Simulation

Vertical organic transistors are an attractive alternative to conventional lateral organic transistors due to their high DC and AC performance [1]. Among them, organic permeable-base transistors (OPBTs) are considered to be promising candidates for low-voltage flexible electronics due to their unique properties. However, their complex structures necessitate a deeper understanding of their operational mechanisms and the underlying physics [2, 3]. Compact models are essential for designing and optimizing integrated circuits (ICs). They are also used to develop and improve new transistor technologies. Analytical modeling of OPBTs based on geometrical parameterization has been reported [4]. A Gaussian DOS charge-based model has also been developed for organic transistors and adapted to OPBTs [5]. Their AC performance have been analyzed quantitatively, paving the way to reach GHz high frequency in organic transistors [6].In this work, we report on the simplification of the complex structure of OPBTs in terms of their DC performance and characteristics. This simplification makes it easier to simulate, analyze, understand, and explain the working principle, optimize, and model OPBTs. We calibrate the TCAD simulation to the fabricated device structure and its characteristics to ensure that the simulation represents the OPBT to validate this simplification. Based on the calibrated TCAD simulation, we demonstrate that the characteristics of fabricated OPBTs with n pinholes (number of pinholes is determined by the density of pinholes) are equivalent to those of n single pinhole OPBTs connected in parallel. This is proved by physical models and arises from the fact that the pinholes are shielded by the base electrode, resulting in no electrostatic interaction known as screening effects between them. Therefore, it appears as multiple pinholes (transistors) have been fabricated in a single device (OPBT). Thus, one needs to analyze, optimize, and model a single pinhole (where the pinhole density determines the performance and specific structural dimension of the single pinhole) from the fabricated OPBTs and multiply its DC characteristics by the number of pinholes. The new simplification and formulation show good agreement with the experimental data of fabricated OPBTs, as well as the results obtained from TCAD simulations and a Gaussian DOS charge-based model. Acknowledgements: This project is funded by the German Research Foundation (DFG) under the grants "DA 2578/2-1" and "KL 2961/10-1", the Spanish Ministry of Science (PRX21/00726), and the EU EIC-PATHFINDER (BAYFLEX, no 101099555).

Impact of deep cryogenic temperatures on gate stack dual material DG MOSFET performance: Analog and RF analysis

By understanding the potential benefits of Gate Stack Dual Material double gate MOSFET (DG MOSFET), this research aims to contribute to the investigation of its electrical characteristics with improved performance and dependability. A detailed investigation is conducted into the temperature dependent electrical properties at different temperatures. A detailed analysis is conducted on the enhanced gate controllability in lower technology nodes and the protection against short channel effects. Together with the DC performances, this research also analyzes the suggested device's analog performance. The device's performance matrix was presented for temperatures ranging from 70 K to 800 K. The results showsthe improvement the drain current, transconductance, and transconductance generation factor(TGF) with decrease in temperature.

A novel gate over source-channel overlap dual-gate TFET with insulator pocket and lateral source contact for optimizing subthreshold characteristic

In this work, we propose a novel hetero-junction hetero-gate-dielectric gate over source-channel overlap dual-gate TFET with an insulator pocket and a lateral source contact (IP-LSC-HJ-HGD-GoSo-DGTFET). In the IP-LSC-HJ-HGD-GoSo-DGTFET, an insulator pocket placed between channel and the right side of source is adopted to suppress the source corner effect which can cause SS to deteriorate. Therefore, an ultra-steep SSAVER of 5.5 mV/dec is obtained within 10 orders of magnitude of IDS. Moreover, IOFF is improved by one order of magnitude when the vertical source contact is replaced by a lateral source contact. Finally, the ION, ION/IOFF, VONSET, and gm of IP-LSC-HJ-HGD-GoSo-DGTFET are 97 μA/μm, 2.8 × 1013, 0 V and 510 μS/μm through the optimization of DC performance, respectively. As for the analog/RF performance, IP-LSC-HJ-HGD-GoSo-DGTFET achieves ƒT of 39 GHz and GBP of 17.3 GHz, respectively. Compared with other GoSo-DGTFETs, the proposed IP-LSC-HJ-HGD-GoSo-DGTFET is a better potential candidate in the application field of ultra-low power integrated circuit.

Hysteresis impact of ferroelectric oxide on double-source vertical tunnel FET: DC and RF performance

Hysteresis impact of ferroelectric oxide on double-source vertical tunnel FET: DC and RF performance

Device and circuit-level performance evaluation of DG-GNR-DMG vertical tunnel FET

This work presents the comparative study of Graphene Nanoribbon (GNR) based channel Double Gate (DG) Dual Gate Material (DMG) Vertical tunnel Field Effect Transistor (VTFET) performance with all Silicon material Tunnel Field Effect Transistor. The two-dimensional (2D) material GNR has been proposed in the channel material to enhance the device performance due to its low bandgap, high mobility, and high saturation velocity. The proposed device's DC, RF, and circuit-level performance analysis has been carried out for the first time. GNR-based channel VTFET shows a better average subthreshold swing (SSAVG) of 16 mV/decade compared to Silicon Vertical Tunnel FET (36 mV/decade) at a drain voltage VDS = 0.5 V. The study of temperature effects on the DC parameters is also included along with the analog/RF FOMs for the proposed two structures. In addition, the performances are compared with other reported works; it is observed that DG-GNR-DMG-VTFET offers better results than Silicon (Si)-based VTFET and other said TFET work. Finally, circuit-level analysis has been done by designing inverter and ring oscillator circuits for the proposed structures, and performance is compared in these two devices. The market-available Silvaco ATLAS TCAD simulator has been used for device-level simulation. Further, circuit-level analysis has been carried out in the Cadence Virtuoso tool using a look-up table-based Verilog-A model.

3-D curved composite façade elements with PV: Results of a pilot project

This paper describes the design, manufacturing, installation and monitoring of a BIPV system that consists of coloured 3D structured façade elements, mounted on an existing office building at the High Tech Campus in Eindhoven. The façade elements contain thin film CIGS modules, which adopt the curved structure of the elements. The encapsulation of the PV modules into the façade elements, the colouration and the curvature led to a relative loss of about 10 % of the efficiency. The PV façade consists of 48 elements with a STC capacity of 5.8 kWp. Each element was equipped with a power optimizer, enabling individual monitoring of each façade element. The elements have been installed at the east and south façade of the building. The monitoring presented in this paper comprised a period of 5 months: the summer and autumn of 2023. The DC performance ratio during that period was 75 % for the elements on the East façade and 80 % for the elements on the South façade; which is in accordance with simplified model predictions. The result is a visual attractive retrofitted PV façade contributing to zero emission strategy of the Eindhoven High Tech Campus.

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

In this work, we systematically investigate the DC performance of fully depleted silicon-on-insulator (FD-SOI) MOSFETs at both room and cryogenic temperatures as low as 77 K. The influences of back-gate bias on normal and flip-well devices are measured and analyzed. Both types devices display non-linear behaviors when adjusting the back-gate voltage at cryogenic temperatures. Notably, the non-linear effects are more prominent in normal-well devices. The possible reasons are analyzed and verified by technology computer aided design simulation, suggesting that normal-well devices are more susceptible to the formation of depletion regions between the buried oxide layer and the well. This phenomenon disrupts the linearity of the back-gate effect. This research contributes to understanding and characterizing of the back-gate effects in cryogenic environments and holds potential for high-performance computing applications.

Hybrid Energy Storage Integrated Wind Energy Fed DC Microgrid Power Distribution Control and Performance Assessment

Hybrid Energy Storage Integrated Wind Energy Fed DC Microgrid Power Distribution Control and Performance Assessment

InAlGaN-based HEMT with very low Ohmic contact resistance regrown at 850 °C by MOVPE

Regrown Ohmic contacts have been widely studied for high millimeter-wave applications. However, few were applied to InAl(Ga)N-based HEMT despite the lattice match benefits with GaN channel because of the poor thermal stability of the quaternary barrier. In this article, we use relatively low temperature (850 °C) MOVPE technique for the regrowth of heavily Si doped GaN (1 × 1020 cm−3) to avoid deterioration of the channel's electrical characteristics. Moreover, high selectivity of the regrowth is obtained, thanks to large opening ratio of the hard mask. The state-of-the-art total Ohmic contact resistance Rc = 0.06 Ω mm is reached with high homogeneity on a 4-in. wafer. This result reflects the combined contribution of the doped GaN interfaces with both the metal contact and the channel. 2 × 50 μm transistors featuring 100 nm gate length with regrown Ohmic contacts present remarkable improvements of DC and RF performances. At 40 GHz, the highest Power Added Efficiency (PAE) of 54% is attained at an output power of 3.8 W mm−1, while the maximum output power of 9.4 W mm−1 is achieved at a PAE of 48%, corresponding to bias voltages of 15 and 30 V, respectively.

DC and RF performance analysis of enhancement mode fin-shaped tri-gate AlGaN/GaN HEMT and MOSHEMT with ultra-thin barrier layer

The DC and RF assessment of critical barrier-AlGaN/GaN nano channel tri-gate fin-shaped High Electron Mobility Transistor (FinHEMT) is investigated for Enhancement-mode (E-mode) operation. We propose and analyze critical barrier layer (CBL) and critical-strained barrier layer (CSBL) FinHEMT for a fixed fin-shaped channel width (W fin = 160 nm) and height (H fin = 70 nm). The CBL FinHEMT ensures an E-mode operation by depleting two-dimensional electron gas (2DEG) near the channel region between AlGaN and GaN hetero-junction. The extracted threshold voltage (V T ) in CBL FinHEMT is 0.4 V as compared to −0.2 V obtained in CSBL FinHEMT. However, increased gate leakage current density and poor gate voltage swing in CBL FinHEMT is improved through a metal-oxide-semiconductor FinHEMT (FinMOSHEMT) structure by the incorporation of Al2O3 gate oxide layer between the tri-gate and CBL AlGaN layer. It results in a stable positive VT of 0.5 V due to the negatively charged Al2O3/barrier interface fixed charge density ( NAl2O3 ). The proposed CBL FinMOSHEMT has also been studied for different atomic layer deposition Al2O3 process-dependent variations in NAl2O3. The maximum on-state drain current and transconductance of 1.01 A mm−1 and 430 mS/mm have been extracted respectively with NAl2O3 of −9.2 × 1012 cm−2. Further, the RF analysis of the proposed CBL FinMOSHEMT structure with the same dimension exhibits improved f T and f max responses with 27 GHz and 90 GHz respectively over CBL FinHEMT. The results of the frequency responses obtained for the proposed design make it suitable for power electronics applications.

Effect of rapid thermal annealing on DC performance of Mg0.30Zn0.70O/Cd0.15Zn0.85O MOSHFET

This study focuses on a cost-effective method for fabrication of a metal oxide semiconductor-heterostructure field effect transistor (MOSHFET) based on MgZnO/CdZnO (MCO) using dual ion beam sputtering (DIBS), in contrast to the more expensive epitaxial growth system. The MOSHFETs developed in this research exhibit notable characteristics, such as a substantial two-dimensional electron gas (2DEG) transconductance (∼2.6 mS), a high ION/IOFF response ratio in the order of 108, and minimal gate leakage current. Furthermore, we explore the impact of rapid thermal annealing (RTA) on the drain current at various temperatures (600 °C and 800 °C). The results indicate a fourfold improvement in drain current compared to unannealed conditions, primarily attributed to reduced contact resistance and no degradation in term of MgZnO/CdZnO structure. Additionally, an analysis of post-RTA treatment under a nitrogen (N2) atmosphere on gate leakage current is presented. The investigation spans temperatures ranging from 400 °C to 800 °C, revealing that above 600 °C (gate leakage at 400 °C–600 °C is around ∼10−9 A), gate leakage in HFET is augmented by one order of magnitude (∼10−8 A) due to a phase change in the dielectric. These findings underscore the feasibility of DIBS-grown MCO MOSHFETs as an economical solution for the mass production of switching devices and sensors.

Impact of eliminating ungated access regions on DC and thermal performance of GaN-based MIS-HEMT

The impacts of eliminating access regions (AR) on DC and thermal performance of GaN-based MIS-HEMT have been studied using a device of 4 µm gate length. Nominal absence of ARs was achieved by a metal-organic chemical vapor deposition-regrown heavily n-doped GaN contact region extended to the two-dimensional electron gas (2DEG) channel (with sheet resistance as low as 14 Ω/ ◻ and ohmic contact resistance of 0.20 Ω⋅ mm) and 22-nm-thick AlN/Al2O3/HfO2 insulator layers acting as both gate dielectrics and sidewall spacers. As a result, a low knee voltage (2.5 V @ VGS = +2 V) comparable to deeply-scaled devices was attained, revealing the dominant role of ARs in knee voltages. High linearity at lower supply voltages (gate voltage swing of 7.3 V @ VDS = 5 V) and a faster GVS saturation trend with V DS increasing were observed, benefiting from the improved utility of applied lateral voltage. Moreover, a much lower thermal resistance compared to that of the conventional MIS-HEMT structure (146 vs. 202 K W−1) was extracted by a static-pulsed I-V measurement method. Simplified TCAD simulations were conducted to explain the underlying mechanisms, demonstrating that the enhanced surface heat flow covered by the gate metal as well as the more uniform electric field along the 2DEG channel accounts for the better capability of heat management in the device free of ARs. Our results indicate the size of DC and thermal performance enhancements obtained by eliminating ARs in a GaN-based MIS-HEMT structure.

Performance improvement of SOI Tunnel-FET using pure boron and Ge pocket layer

This article highlights the results of a source pocket-engineered heterojunction pure-boron SOI Tunnel-FET (SP-PB-TFET) for low-power applications. To achieve improved performance, a novel pure-boron silicon TFET structure is considered with Silicon–Germanium source, Germanium pocket. Based on experimental data, the on-state current of a SiGe source TFET increases with increasing Ge content in SiGe. Nevertheless, the off-state leakage current increases with the Ge content of SiGe. To mitigate the problem somewhat, a Ge-pocket could be incorporated into the source near the tunneling junction. The final results provide a high current ratio (Ion/Ioff) of 1011 and a steep subthreshold swing (SS) of 18 mV/Decade at a very low supply voltage of 0.7 V. Moreover, SP-PB-TFET is suitable for high-frequency appliances due to its high cut-off frequency. This work also addresses the impact of temperature analysis and interfacial traps on device performance. The proposed SP-PB-TFET provides excellent DC and analog performance, making it suitable for low-power, high-frequency applications.