DC Offset Voltage Research Articles

Grid synchronization method based on three novel types of third-order generalized integrators

Phase-locked loop (PLL) is widely used to estimate synchronous information such as amplitude and phase angle of grid voltage. It plays a crucial role in distributed renewable energy grid-connected power generation. However, the presence of grid harmonics and DC offset voltage (DCOV) can affect the accurate extraction of the fundamental voltage component, leading to phase-locked deviation. This paper introduces three novel or improved third-order generalized integrators (TOGI) with DCOV rejecting function to address this issue. A unified dual third-order generalized integrator (DTOGI) structure is designed based on the three TOGI structures. This DTOGI structure is further combined with a moving average filter (MAF) to propose three innovative three-phase PLLs. Unlike other PLL filtering methods that inadequately consider DCOV, the proposed PLL methods not only reject DCOV but also eliminate the fundamental voltage negative sequence component (FVNSC) and each order harmonic component. They demonstrate strong robustness and excellent filtering performance even under abnormal grid conditions. Among the three methods, the DII-TOGI based PLL exhibits superior dynamic performance compared to the other two methods, it can improve dynamic characteristics by about 10 % compared to the other two methods. The effectiveness of the proposed methods is verified through extensive Matlab/Simulink simulations and experiments.

Research on a New Synchronous Phase-Locked Method for Renewable Energy Grid-connected Converters

Background:: The phase-locked loop (PLL) is widely used to estimate synchronization information such as magnitude and phase angle of the grid voltage, which is essential for gridconnected power generation from distributed renewable energy sources. However, the harmonics in the grid often affect the accurate extraction of fundamental positive sequence, resulting in phase deviations. Methods:: A dual extended novel third-order generalized integrator (DENTOGI) is proposed and placed into the control outer loop of the PLL. This approach can be applied in the condition of the grid with DC offset voltage (DCOV). Additionally, the PLL is proposed by introducing moving average filter (MAF) and eliminating the proportional controller of the integration link to suppress high-frequency harmonics and speed up the response. Results:: A comparative experiment using Matlab/Simulink is conducted to evaluate the proposed PLL against the conventional PLLs. The experimental results confirm that the proposed PLL exhibits superior filtering performance for DC offset and harmonic components when compared to the conventional PLL. Additionally, the proposed PLL demonstrates better dynamic adjustment capabilities. Conclusion:: The main contribution of this paper is to propose a phase-locked method that can eliminate DCOV and harmonic components, which can be applied in non-ideal power grid conditions. The proposed PLL based on DENTOGI and MAF can lock the grid phase stably without errors under the grid fault involving DCOV and harmonic disturbance, it also exhibits the characteristics of fast response.

A 0.26 [formula omitted]Vrms instrumentation amplifier based on discrete-time DC servo loop with successive-approximation-compensation technique and Chopper DAC Array

A low-noise instrumentation amplifier for bio-signal recording is proposed in this paper. One of the significant disturbances, electrode DC offset, is suppressed using the proposed successive-approximation-compensation (SAC) circuit based on a discrete-time DC servo loop with Chopper DAC Array. Firstly, the DC offset at the output is quantified using the SAR quantizer. Next, the digital code produced by the SAR quantizer is used to control the chopper DAC array. Finally, a suitable compensation voltage is generated and used directly to correct the electrode DC offset at the input of the chopper amplifier. By using the proposed compensation technique, the first-stage chopper amplifier’s quiescent operating state is unaffected. When a 50-mV DC offset voltage exists at the differential input, the SAC circuit can compensate the DC offset voltage close to zero in a relatively short time. At the same time, there are fewer capacitors, which significantly decrease the area consumption. The proposed instrumentation amplifier is implemented in a standard 0.18μm CMOS process. The experiment results show that over a bandwidth from 0.1 Hz to 100 Hz, an input referred noise of 0.26 μVrms at the TT corner has been attained. The total power consumption is about 13.72 μW at the supply voltage of 1.8 V. The gain of the instrumentation amplifier is about 39.15 dB and its Noise Efficiency Factor (NEF) is 2.76.

Fault Detection and Ride Through of CHB Converter-Based Star-Connected STATCOM Through Exploring the Inherent Information of Multiloop Controllers

A simple detection and ride-through operation approach is proposed for star-connected cascaded H-bridge (CHB) converter-based STATCOMs with a single IGBT open circuit fault. It adopts a modified current regulator with high gains at both dc and fundamental frequencies. Then, the output signals of the current regulator branches and the dc voltage balancing regulator are synthesized as an inherent indicator to quickly determine the position of the open-circuit fault IGBT. With this approach, the controller can also be considered as an inherent system state monitor, but without any additional sensors or computing burdens. Afterwards, in the ride-through operation stage, the faulty H-bridge module can switch to half-bridge operation and the corresponding dc offset voltage is compensated by the remaining healthy modules. It has been validated that the proposed approach is accurate in various conditions, including grid voltage and load disturbances.

Online Diagnosis and Ride-Through Operation for Cascaded H-Bridge Converter Based STATCOM With a Single Open-Circuit IGBT

To address the most commonly seen single insulated gate bipolar transistor (IGBT) open-circuit fault problems in cascaded H-bridge (CHB) converter based static synchronous compensator, a simple online fault diagnosis method and the corresponding ride-through operation approach are proposed. The method can quickly determine the exact location of the open-circuit IGBT through three steps, via analyzing the relationships between the dc bias in the three-phase output current of CHB converter, the transient dc rail voltage variations with respect to the averaged dc rail voltage, and the response of dc rail voltage and output current when the modulation approach of the faulty power module is adjusted. Afterwards, a fault ride-through approach is adopted to seamlessly transfer the modulation approach of faulty H-bridge module and it behaves as a half-bridge to provide a half of the rated output ac voltage. Meanwhile, the corresponding dc offset voltage from this faulty module is compensated by producing the same dc voltage in the healthy phase legs to avoid the dc bias in the three-phase output current. It has been demonstrated that the proposed fault diagnosis approach and the fault ride-through approach are effective in various adverse situations including grid voltage sudden disturbances and the load power sudden changes. Comprehensive simulated and experimental results have been provided to validate the effectiveness of the proposed approach.

Design of low offset voltage in second stage CMOS operational amplifier using 90nm technology

In this paper a low offset voltage; low power and high gain second stage op-amp of differential amplifier along with common source amplifier with compensated capacitor is proposed. The mathematical analysis of two-stage op-amp is elaborated and this work is compared with exiting similar work. The experimental work carried in CADENCE Virtuoso with 0 gpdk090 process technology is used to obtain 60.994 of Phase Margin, 61 dB DC gain and Offset voltage is 2mV. The M/L ratios are selected accordingly where supply voltage and load voltage are fixed at 1.8V and 12pF respectively. The parametric analysis helps, where the values are fixed to get better response.

A novel phase estimation method for renewable energy grid-connected equipments

When renewable energy is applied to the power grid, it will cause problems such as harmonic interference and changes in grid frequency, resulting in harmonic distortion of the inverter and other renewable energy grid-connected equipments output current. So the grid-connected environment of weak grid puts forward higher requirements on the performance of phase-locked loop (PLL). Therefore, these renewable energy grid-connected equipments require Phase-Locked Loop (PLL) with higher technical performance. Aiming at the control requirements of inverter and other grid-connected equipments in weak grid, an optimization method based on a novel PLL is proposed. The method uses a dual enhanced novel cascade second-order generalized integrator (DENCSOGI) to simultaneously filter out the fundamental voltage negative sequence (FVNS) component and the DC offset (DCO) voltage component, and it can speed up the dynamic response and phase-locked accuracy of the PLL. The proposed PLL is verified by the simulation experiment platform. The performance of the approach is excellent and the grid-connected power quality of the renewable energy grid-connected equipments is guaranteed.

A New Structure of 8-Bit 60 MS/s SAR-ADC Using a Reduced Switching Capacitor-DAC Array

This paper presents an analysis of the Reduced Switching Capacitor Digital-to-Analog Converter (RSC-DAC)-based low power Successive Approximation Register Analog to Digital Converter (SAR-ADC). The proposed structure involves the Low voltage Static D-Latch Comparator (LSD-LC) with pre-amplifier operators in two modes (Normal and Hold), the RSC-DAC switching energy, reduced by 93% contrast to the standard Charge Redistribution Switching Capacitor DAC (CRSC-DAC) method, and the Successive Approximation Register (SAR) control logic. The LSD-LC with pre-amplifier consists of a latch circuit and a pre-amplifier. The pre-amplifier is often used to eliminate the DC offset voltage and kickback noise without substantially weakening the Signal-to-Noise Ratio (SNR) to drive the main circuit while the latch is needed for comparison. The linearity parameters such as Integral Nonlinearity, Differential Nonlinearity and effect of parasitic capacitances of the RSC-DAC are analyzed and improved by the new approach named as Adaptive Random Code Generation (ARCG) Technique. The above overall design is implemented in 250-nm CMOS design of the TANNER-EDA tool, consuming 1.74-mW power at 60[Formula: see text]MS/s. The proposed structure has an INL and a DNL, respectively, of +0.18/[Formula: see text] LSB and +0.11/[Formula: see text]0.05 LSB.

Versatile AC Current Control Technique for a Battery Using Power Converters

Although a battery is a DC device, AC current is often necessary for testing, preheating, impedance spectroscopy, and advanced charging. This paper presents a versatile control technique to inject AC current to a battery. Synchronous buck and H-bridge topologies are operated in bidirectional mode and controlled by uni-polar and bi-polar pulse width modulation techniques for the AC current injection. The input and output passive circuits are specially designed considering AC current and the properties of the battery. A controller is proposed considering a small internal impedance, small AC ripple voltage, and variable DC offset voltage of a battery. The controller is capable of maintaining stable operation of AC current injection in two power quadrant within a small DC voltage boundary of a battery. The controller is comprised of a feedback compensator, a feedforward term, and an estimator. The feedback gain is designed considering the internal impedance. The feedforward gain is designed based on estimated open circuit battery voltage and input voltage. The open circuit voltage estimator is designed based on filters and battery model. For validation, AC current is injected to a Valence U-12XP battery. The battery is rated for 40 Ah nominal capacity and 13.8 V nominal voltage The controller successfully injected AC current to a battery with +10 A, 0 A and −10 A DC currents. The magnitude and frequency of the AC current was up to 5 A and 2 kHz respectively.

Elimination of circulating current in parallel operation of single phase inverter using droop controller

This paper presents the control strategy for parallel operation of an inverter to eliminate DC & AC circulating current. This paper also analyses the cross-current between parallel connected inverter due to the difference in output voltage magnitudes of inverters, the phase difference of inverter output voltages and difference in DC offsets present in inverter output voltages. The circulating current flows between inverters due to DC-offset voltage and fluctuation of AC output voltages. This strategy uses the fundamental voltage and phase droop scheme to allow the inverters to share their load currents and uses a DC-offset droop scheme in order to eliminate DC circulating current. AC component of current is divided into two parts i.e. an active component of the current Ip and a reactive component of the current Iq. These two components of AC currents are used to eliminate AC circulating current. The validity of the proposed control strategy is investigated through MATLAB simulation and the results obtained satisfactorily.

Output Voltage Imbalance Compensation Using dc Offset Voltage for Split dc-Link Capacitor 3-Leg Inverter

In this paper, we analyzed the output voltage imbalance and the cause of the offset voltage in 3-phase 3-leg inverters by using Millman’s theory. Based on this result, we proposed a voltage imbalance compensation algorithm using the dc offset voltage that appeared at the neutral point voltage of the load. To apply the proposed imbalance compensation algorithm, it needs a circuit structure of 3-phase 4-wire such as split dc-link capacitor 3-leg inverter and 4-leg inverter. Therefore, the total harmonic distortion (THD) of the load phase current according to the imbalance rate of the load was analyzed for the two inverters. Then, PSIM simulation and experiments based on a 10 kW-prototype of split dc-link capacitor 3-leg inverter were implemented to verify the validity of the proposed imbalance compensation algorithm.

Phaselet-Based Limited-Time $q$-Axis DC Offset Voltage Injection for Detection of Islanding of DG and Fault in a Meshed Microgrid

Rapid grid integration of inverter-interfaced distributed generators (DGs) and low-voltage ride-through capability of the smart inverter, as per IEEE 1547 standard, has made unintentional islanding detection (UID) cumbersome. Also, the feeder reconfiguration capability in meshed microgrids with multiple DGs has made the existing UID techniques ineffective. The methods have limitations in UID for small power mismatch conditions characterizing nondetection zone (NDZ). In hybrid methods for UID, a disturbance injection is continuous or for an extended period, which degrades the power quality (PQ) and creates stability issues. Hence, a decentralized closed-loop hybrid islanding detection method (HIDM) based on the indices extracted from the subcycle phaselet (passive) technique with limited-time (only for two cycles) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$q$</tex-math></inline-formula> -axis dc offset voltage injection (active) is proposed for UID of DGs. The proposed HIDM mitigates the NDZ due to the closed-loop scheme. Subcycle estimations from the phaselet technique result in quick UID and fault detection and classification process. Furthermore, the PQ issue is reduced due to the limited-time voltage injection (based only on the command from phaselet technique) in the proposed HIDM. Simulation results from the real-time digital simulator on a meshed microgrid and performance comparison with other existing methods prove the efficacy of the proposed HIDM.

DC offset elimination method of Phase-locked loop based on novel generalized integrator

When the renewable energy power is connected to the grid, distortion voltage interference and grid voltage frequency fluctuation will occur, which will cause the inverter output current to be abnormal. So the grid-connected environment of weak grid puts forward higher requirements on the performance of phase-locked loop (PLL). The synchronous reference frame PLL(SRF-PLL) has become a usually adopted method in grid synchronization technique for its simple structure and strong stability. However, the conventional SRF-PLL has insufficient capability to suppress DC offset, which easily causes fundamental frequency and phase oscillations. Therefore, this paper presents a novel generalized integrator(NGI), and according to the presented NGI structure, a modified novel generalized integrator (MNGI) that can eliminate DC offset voltage is proposed. Then a novel PLL based on dual MNGI(DMNGI) is proposed. This method improves the capability of the phase-locked loop to suppress DC offset. At the same time, this paper designs the parameters of the PLL, and the rationality of the novel PLL is tested effectively through the experimental comparison with the other two methods.

Flexoelectric Effect on Image Sticking Caused by Residual Direct Current Voltage and Flicker Phenomenon in Fringe-Field Switching Mode Liquid Crystal Display

Although transmittance changes like a quadratic function due to the DC offset voltage in FFS mode LCD, its bottom position and flicker minimum DC offset voltage varies depending on the gray level due to the flexoelectric effect. We demonstrated how the influence of the flexoelectric effect changes depending on the electrode width or black matrix position.

A fabrication of a low-power low-noise neural recording amplifier based on flipped voltage follower

In this work, a fabrication of low-voltage low-power and low-noise neural recording amplifiers are presented. An operational transconductance amplifier (OTA) was built using the flipped voltage follower (FVF). The low noise operation is achieved without increasing the bias current of the input transistors or decreasing the aspect ratio of the output transistors, which leads to large overdrive voltage.This proposed OTA is used to build a biopotential amplifier using AC coupling technique to achieve one of the lowest noise efficiency factor (NEF) of 2.13. This bioamplifier is fabricated using UMC 130 ​nm CMOS process and the measurement results are obtained. The proposed OTA is also used to design a second biopotential amplifier using active low-frequency suppression technique to achieve one of the lowest occupied area of 0.047 ​mm2 while maintaining a reasonable Noise efficiency factor (NEF) of 4.27. The active low-frequency suppression technique is used to reject the DC offset voltage while preserving high input impedance and small area. The first bioamplifier consumes 2.2 ​μA from 1 ​V supply voltage. The input-referred noise is 3.7 μVrms. The bandwidth (BW) ranges from 25 ​Hz to 9.9 ​kHz. The achieved noise efficiency factor (NEF) is 2.13. The dynamic range is 55 ​dB. It occupies a silicon area of 0.112 ​mm2. The second bioamplifier consumes 5.2 ​μW from 1 ​V supply voltage. The input-referred noise is 4.7 μVrms. The BW ranges from 110 ​Hz to 9.7 ​kHz. The achieved NEF is 4.27. It occupies an area of 0.047 ​mm2.

Nonlinear out-of-plane resonation of a circular dielectric elastomer

A dielectric elastomer (DE) membrane can generate nonlinear out-of-plane vibrations under an alternating voltage. The generation mechanism and vibration characteristics were investigated in this paper. Multi-order superharmonic resonance occurred as the AC voltage increased. After the introduction of DC offset voltage, both superharmonic and subharmonic resonance occurred. The frequency characteristics of the superharmonic resonance with and without DC voltage were different. The nonlinear out-of-plane vibration characteristics can be potentially harnessed in a DE vibration-driven system.

Enhanced Grid-Connected Phase-Locked Loop Based on a Moving Average Filter

Moving average filter (MAF)-based phase-locked loops (PLLs) have received considerable attention in recent years due to their attractive features. Indeed, they are able to completely eliminate the unwanted effect of harmonics, dc offset, and unbalanced voltages. Unfortunately, these advantages come at the cost of open-loop bandwidth reduction, which worsens the system's dynamic response. The main challenge is to estimate the phase and frequency timely and precisely from an imbalanced and distorted voltage. In addition, optimized parameter design is also a difficult issue. The main aim of this paper is to present an enhanced PLL based on a moving average filter (EMAF-PLL) and a control method with a novel compensation algorithm. The EMAF-PLL can maintain high performance even under harsh grid conditions, and the novel control method enables the designer to set the controller parameters simply and effectively. The design method compensates the PLL small-signal model to form a type-II classic system and then optimizes the control-loop design by the rules of type-II systems. Finally, experimental investigations are performed to validate the effectiveness of the EMAF-PLL. The experimental results are also presented, and comparison with conventional PLLs verifies that the dynamic performance can be significantly improved.

Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System

This brief presents a vital-sign processing circuit for simultaneous dc/near-dc elimination and out-of-band interference rejection without any digital signal processing or algorithm assistance for the ultrawideband (UWB) pulse-based radar system. An intrinsic self-balanced MOS diode (SBMD) was proposed as a stable and balanced pseudo resistor applied under a servo feedback loop in a vital-sign receiver of the sensing radar to perform as a high-pass filter (HPF) with an ultralow corner frequency lower than 0.5 Hz for removing undesired clutters of the reflected signals and input dc-offset voltages from innate circuit offsets. A third-order switched-capacitor (SC) Chebyshev low-pass filter (LPF) with leap-frog topology as the subsequent stage was adopted to suppress the out-band noises, thereby establishing an integrated vital-sign processing circuit with bandpass frequency response and incorporating it into a radar module to verify its viability.

Passive Impedance Matching for Implanted Brain–Electrode Interfaces

We propose a new technique for matching the high impedance of sub-cranial electrodes to wireless brain implants that is passive, highly tolerant of the dc offset voltage caused by the electrochemical reaction in the recording electrode, and complemented by an improved external interrogator design that exhibits reduced phase noise. As compared to previous wireless and batteryless brain implants, the proposed approach offers a remarkable improvement in sensitivity by 25 times. The proposed system consists of an external interrogator and a neuro-recorder implanted under the scalp. For operation, the interrogator sends a 2.4-GHz carrier signal to turn on the implant. This carrier self-biases a PNP Bipolar Junction Transistor (BJT) that enables matching to the recording electrode at frequency $f_{neuro}$ in a batteryless manner. Concurrently, the recorded neuropotentials (at frequency $f_{neuro}$ ) pass through a Schottky diode that allows them to mix with the carrier and generate a 4.8 $\text{GHz}\pm f_{neuro}$ modulated signal. The latter is then transmitted back to the interrogator for demodulation. To verify the implant's operation, in-vitro measurements are presented. Measurement results demonstrate that emulated neuropotentials as low as 200 $\mu V_{pp}$ can be detected at a 33- $\text{k}\Omega$ electrode impedance. As such, the proposed system presents a game-changing capability for a wide range of applications.

High-CMRR Low-Noise Fully Integrated Front-End for EEG Acquisition Systems

We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR achieved in this work is a result of cascading three amplification stages to construct the LPGA in addition to the lower common-mode gain of the proposed logarithmic amplification topology. In addition, the 1 / f noise and the inherent DC offset voltage of the input transistors are reduced using a chopper stabilization technique. The CMOS 180 nm standard technology is used to implement the circuits. Experimental results for the integrated LPGA show a CMRR of 140 dB, a differential gain of 37 dB, an input-referred noise of 0.754 μ Vrms, a 189 μ W power consumption from 1.8 V power supply and occupies an active area of 0.4 mm 2 .