DC Offset Voltage Research Articles

Three Carrier PWM Control of Improved Z-Source Inverter

A kind of three carrier PWM control method is put forward for improved Z-source inverter. The switches are controlled by comparing three carrier and three reference waves. The shoot-through zero state are injected in the time when traditional zero vector worked. The voltage gain is determined by the dc offset voltage of carrier wave when the modulation index is constant. Boost factor is made independent of the modulation index. And the switching loss is reduced. The voltage stress on the capacitances and switches are analyzed in detail. Simulation results show that this method possesses better control performance.

Wireless Sensor Networks and the Internet of Things

It is estimated that mobile internet devices that can act as sensors will outnumber humans this year (2013), and by 2015, there will be about 15 billion internet-connected devices. Related applications are thriving in commercial, civic, and scientific operations that involve sensors, web, and services, leading by both academic societies and industry companies. It is commonly accepted that the next generation of internet is becoming the “Internet ofThings (IoT)”which is a worldwide network of interconnected objects and their virtual representations uniquely addressable based on standard communication protocols. Identified by a unique address, any object including computers, mobile phones, RFID tagged devices, and especially Wireless Sensor Networks (WSN) will be able to dynamically join the network, collaborate, and cooperate efficiently to achieve different tasks. With all these objects in the world equipped with tiny identifying devices, daily life on earth would undergo a big transformation. To achieve this vision, there is a need for scalable and interoperable networking systems to support the challenging requirements for future internet and web: secure, reliable, energy-efficient and cost-effective large-scale sensor networks, machine-to-machine communications, and information networking architectures suitable for low end devices through to high end consumers. The purpose of this special issue thus is to report on the recent and original advances on WSN and IoT that are to be innovative to open the new era of the Internet ofThings. From the many submissions we received, a number of exciting manuscripts stood out for their relevance and technical significance.These accepted papers touched upon threeWSN and IoT areas: IoT network infrastructure, related hardware design, and IoT protocols. A. Asensio et al. discussed the wireless sensor node architecture hardware design criterion based on energy analysis according to the specific requirements of an application. C. Liu et al. proposed a novelWSNauthentication scheme based on the quadratic residues theory, which uses themaster key to achieve simple symmetric cryptographic primitives and authentication operation for aims of great resistance against the attacks and low energy consumption. F. T. Lin proposed a method to tackle the dying nodes as well as the cost, specifically a holes healing scheme. C. Xu proposes a novel Vehicular Network-based CMT solution based on a CMT disorder analytic model which can effectively and accurately evaluate the degree of out-of-order data. S. Yin proposed two digital calibration and compensation techniques for low-power wireless multiband transceiver to adjust the VCO’s tuning curves in the frequency synthesizer and eliminate the DC offset voltage in the intermediate frequency pathway. J. Zhang proposed an energy-efficient distributed algorithm for virtual backbone construction with cellular structure WSN, which combines optimal coverage theory based on cellular structure and energy consumption model for different kinds of sensor nodes to achieve the construction and rotation of backbone in multiple rounds. By compiling these papers we hope to enrich our readers and researchers with latest innovative ideas with respect to the future Wireless Sensor Network and Internet of Things.

Calibration Techniques for Low-Power Wireless Multiband Transceiver

The low-power wireless transceiver is the basic silicon building block of wireless sensor networks and the internet of things. In this paper, two digital calibration and compensation techniques for low-power wireless multiband transceiver are presented to adjust the VCO's tuning curves in the frequency synthesizer and eliminate the DC offset voltage in the intermediate frequency (IF) pathway. The fuzzy binary search method is applied to VCO calibration, and gain-based DC offset cancellation (DCOC) is applied. Based on these proposed methods, a multiband transceiver is designed and fabricated in 0.18 μm CMOS with 1.8 V voltage supply. Experimental results show that with 24 MHz system clock, frequency synthesizer calibration can be completed within 450 without requiring any additional calibration prescaler, achieving a calibration resolution of 1 MHz; DC offset voltage can be reduced to less than 3.5 mV for 0 to 60 dB gain, with each calibration process taking only 1.28 ms time. The proposed techniques and corresponding circuits are proved to be cost-efficient while maintaining high performance, which is suitable for multiband and multimode transceiver integration.

A High Speed-Low Power Comparator with Composite Cascode Pre-amplification for Oversampled ADCs

This paper presents a high speedlow power CMOS comparator using composite cascode differential pair as a pre-amplification stage. The purpose of this work is to design a comparator for oversampled ADC application. This comparator is designed using 180nm CMOS technology with a power supply of 1.2V. Pre and post layout simulation of the proposed circuit is done using cadence tool. The total power consumption of the comparator is 71.61μW and unity gain-bandwidth is 1GHz. The DC offset voltage is 12mV, gain is 70dB while total area occupied by comparator is 684μm 2 . This design achieves an OSR (Oversampling Sampling Ratio) greater than 1000 which corresponds to SNR improvement of 30dB for Σ-Δ converters. 

Modelling electroluminescence in insulating polymers under ac stress: effect of voltage offset and pre-stressing

Ac electroluminescence (EL) in polyethylene films is well documented on experimental grounds but a detailed model encompassing injection and transport is still to be strengthened. In particular, different papers report that the EL under ac sinusoidal voltage for both divergent and uniform field configurations is independent of a superimposed dc voltage offset, which is confirmed by our own measurements. Based on modelling, we show that the dc offset voltage induces a transient behaviour of the ac EL; where the symmetry between the EL peaks occurring during each half cycle of the ac voltage is broken but the same steady state is reached for any value of dc offset. The transient duration is short relative to the timescale of a typical EL measurement explaining why it has not been reported experimentally. It depends on the injection level, charge mobility and recombination efficiency. The model also explains the dependence of ac EL on the presence of homo-space charge near the electrodes.

A novel compact low-power direct conversion receiver for mobile UHF RFID reader

A novel direct conversion receiver with low cost and low power is implemented in a 0.18 μm 1P6M standard CMOS process for a Mobile UHF RFID reader. A highly linear active mixer with low flicker noise and low noise active load is proposed. An efficient and low cost on-chip DC offset voltage canceling scheme is adopted with a high-input-impedance four-input OPAMP to buffer the output of the DC offset canceller (DCOC) block. The receiver has a measured input 1 dB compression point of −2 dBm and a sensitivity of −72 dBm in the presence of the large leakage signal from the transmitter. Only occupying a silicon area of 2.5 mm2 and consuming 21 mA from a 1.8 V supply, the receiver makes the mobile UHF RFID reader to communicate with a transponder in a distance of 1 m conveniently.

Experimental research on hysteresis effects in GMR sensors for analog measurement applications

A Wheatstone bridge GMR sensor can be used for analog magnetic field measurements. This paper deals with hysteresis effects in GMR sensor, which is the major source of measurement error. Experiments are conducted by measuring hysteresis curves between applied magnetic field and sensor output voltage with different typical initial magnetization states. GMR sensor has two operation modes: bipolar and unipolar. Bipolar operation means internal magnetization pattern of GMR sensor changes direction during operation range. This mode is inappropriate for direct measurement, as experimental results indicate that the shape of measured curves with the same range of applied magnetic field may be severely distorted due to different initial magnetization states. Unipolar operation is an intermediate process of bipolar operation with invariant magnetization direction. Its input–output relationship is almost linear that is especially suitable for measurement. The principal measurement error within unipolar operation is DC offset voltage, which is induced by remanence. It can be fixed by saturating GMR sensor before operation.

A 0.2–2.6 GHz Wideband Noise-Reduction Gm-Boosted LNA

This letter presents a wideband low-noise amplifier (LNA) which utilizes g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosted and noise-reduction techniques. The proposed DC-coupled 2-stage LNA employs an error amplifier to cancel the DC-offset voltage between the differential DC-coupled paths. The LNA is implemented in 90-nm digital CMOS technology. Within 0.2-2.6 GHz wideband applications, the LNA achieves 24 dB voltage gain, 1.9-2.9 dB NF, - 3 dBm IIP3. The core power of the LNA draws 9 mA from 1V supply voltage and occupies 0.046 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

MOBILE COMMUNICATION APPARATUS

A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

Sinusoidal, Pulse, Triangular Oscillator Using Second Generation Current Conveyor

This paper describes the sinusoidal, pulse, triangular oscillator using second generation current conveyor. To obtain the sinusoidal waveform the circuit blocks are constructed by using all pass filter and integrator. The pulse and the triangular waveforms are obtained from the output of sinusoidal oscillator. The peak-to-peak voltages of sinusoidal and triangular waveforms can be easily controlled by the dc offset voltage. Also the output frequency of the oscillator can be controlled by varying passive elements. The designed circuit is verified by HSPICE simulation.

DC-Offset Compensation Concept for Monostatic FMCW Radar Transceivers

A novel dc-offset compensation technique for monostatic frequency-modulated continuous-wave (FMCW) transceivers is presented. This approach uses the intermediate frequency (IF) port of the active direct-conversion mixer to access its collector resistors. Additional external variable resistors in parallel connection can vary the total load resistance in each branch and hence compensate or generate a dc-offset voltage at the output. Since the wiring is located on the low-frequency side of the mixer, the variable resistors can also be external (off-chip), which offers great flexibility and eases application. The concept was successfully tested with an integrated 77 GHz automotive radar mixer fabricated in a 200 GHz fT Silicon Germanium (SiGe) bipolar technology.

A Neural Recording Amplifier with Low-Frequency Noise Suppression

To detect neural spike signals, low-power neural signal recording frontend circuits must amplify neural signals with below 100µV amplitude and a few hundred Hz frequency while suppressing a large DC offset voltage, 1/f noise of MOSFETs, and induced noise of AC power supply. To overcome the problem of unwanted noise at such a low signal level, a low-noise neural signal detection amplifier with low-frequency noise suppression scheme was developed utilizing a new autozeroing technique. A test chip was designed and fabricated with a mixed signal 0.18-µm CMOS technology. The voltage gain of 39dB at the bandwidth of the neural signal and the gain reduction of 20dB at AC supply noise of 60Hz were obtained. The input equivalent noise and power dissipation were 90nV/root-Hz and 90µW at a supply voltage of 1.5V, respectively.

Direct current offset controller for transformerless single-phase photovoltaic grid-connected inverters

Limitation of direct current (DC) injection into the alternating current (AC) network is an important operational requirement for grid-connected photovoltaic (PV) systems. One way to ensure that this requirement is met is to use a power transformer as interface to the AC network. But this adds costs, mass, volume and power losses. In a transformerless system, the inverter forming part of the PV system has to be operated so that the DC content in its output current is below the specified limits. Ideally, there should be no DC at the output of the inverter, but in practice, in the absence of special measures, a small amount of DC current is present. A technique for elimination of the DC-offset is proposed. It is based on the sensing of the DC-offset voltage at the output of the inverter. A sensor output is used to drive a feedback system designed to control the operation of the inverter so that the DC-offset is forced to stay within the acceptable limits. A mathematical model for the DC-offset controller is derived. A design procedure, based on the model, is proposed for the controller. The results of tests performed on a system of 1 kW nominal rating provide validation for the mathematical model.

A Low-Offset Low-Noise Sigma-Delta Modulator With Pseudorandom Chopper-Stabilization Technique

This paper presents a low-offset low-noise sigma-delta modulator with pseudorandom chopper-stabilization technique. The comparison of the noise-cancellation ability with the correlated double sampling and chopper-stabilization techniques is demonstrated; also, the noise performance of these cancellation techniques is observed and discussed. Using the proposed technique, the modulator achieves 92 dB of dynamic range and -135 dB of noise floor while consuming 950 ¿W from a 3-V supply. Based on the experimental results, the pseudorandom chopper-stabilization technique has a DC offset voltage that is 6 dB lower than that of the chopper-stabilization technique, and retains a thermal noise floor that is 1.6 dB lower than that of the correlated double sampling technique.

Temperature Dependence of Current Gain, Ideality Factor, and Offset Voltage of AlGaAs/GaAs and InGaP/GaAs HBTs

This paper elucidates the stabilities of the dc current gain, ideality factor, and offset voltage against variations in temperature and currents for GaAs-based heterojunction bipolar transistors (HBTs). The InGaP/GaAs HBT markedly reduces the offset voltage and improves the temperature stability of the dc current gain relative to those of AlGaAs/GaAs benchmark devices. The relative insensitivity of the offset voltage in the InGaP/GaAs HBT to the temperature is established by comparison with AlGaAs/GaAs counterparts. One of the more intriguing aspects of these two HBTs is the replacement of the AlGaAs emitter with the InGaP emitter to improve the temperature stability of the offset voltage. Specifically, the effect of the base current on the offset voltage is abnormal in these devices. In this paper, the conventional Ebers-Moll model cannot account completely for our observed phenomena. Accordingly, the results herein (improved temperature stability of the offset voltage in the InGaP emitter HBT and the uncommon base current effect in these two devices) are interpreted in terms of a physics-based analytical model. A strong consistency existed between the experimental data and the theory. Additionally, some reasonable predictions (not obtained from the measured data) of the specific physically based model are presented. The large-signal model provides a description of device performance that will be of use to device engineers and designers.

Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package

A new hybrid modeling method is proposed for the chip-package co-modeling and co-analysis. This method is designed to investigate the simultaneous switching noise (SSN) coupling paths and effects on the dc output voltage offset of the operational amplifier (OpAmp). It combines an analytical model of the circuit with a power distributed network (PDN) and interconnection models at the chip and package substrate. In order to validate the proposed model, CMOS OpAmp was fabricated using TSMC 0.25 mum. Then the dc output offset voltage of the OpAmp was measured by sweeping the SSN frequency from 10 MHz up to 3 GHz. It was successfully demonstrated that the experimental results are consistent with the predictions generated using the proposed model. We also confirmed that the dc offset voltage is strongly dependent on the SSN frequency and the PDN impedance profile of the chip-package hierarchical PDN. It shows the necessity for the chip-package co-modeling and simulation of the system-in-package designs.

Ion Transport in a Reflective Liquid-Crystal-on-Silicon Microdisplay Cell

A built-in potential exists in the reflective liquid-crystal-on-silicon (LCoS) microdisplay cell due to the work-function difference between the aluminum and indium–tin-oxide electrodes. As a consequence, the flicker is generated unless the dc offset voltage is applied to compensate the built-in potential. In this paper, we present the experimental result that the dc offset voltage changes with time as the display is operated and the ions are generated in the liquid crystal (LC). To understand the experimental result, we simulate the ion motion in the LCoS cell by considering both the drift and diffusion. We discuss how the ion concentration in the LC affects the screening of the internal electric field in the bulk LC region and subsequently the built-in potential in the LCoS cell. We show that for an ion concentration higher than the value required to fully compensate the initial built-in potential, the polarity of the built-in potential is changed due to the high electric field near electrodes. By matching the experimental and simulation results, we predict how the ion concentration in the LC increases as a function of operation time.

Temperature dependence of residual DC voltage and its evaluation parameter related to liquid‐crystal and alignment‐layer materials

Abstract— The temperature dependence of residual DC voltage was studied based on the adsorption and desorption of ions in the liquid‐crystal (LC) layer to and from the interface between the LC and alignment layers during the application of an external DC offset voltage. The relaxation process of the adsorbed ions during the open‐circuit state was also studied after applying the DC offset voltage. Those processes were found to follow the Arrhenius rule, and a new evaluation parameter related to the temperature is proposed for the design of the LC and alignment‐layer materials.

A low voltage bootstrapped switch based on zero DC offset input voltage

This paper presents an enhancement to the bootstrapped switching circuit by improving the input range limitation for applying direct input with no dc offset voltage. Application of a Darlington pair in the structure of the conventional bootstrap circuit allows for proper operation of circuits requiring low supply voltage and direct high input swing signal with no dc offset voltage. The proposed circuit is simulated using HSPICE and 0.18µm CMOS technology. Total Harmonic Distortion (THD) measurements results in SNR values which meet the necessary performance requirements for low-voltage application of switched capacitor circuits.

Novel HDD-type SNDM ferroelectric data storage system aimed at high-speed data transfer with single probe operation

In this study, several read/write tests were conducted using a novel ferroelectric data storage test system equipped with a spindle motor, targeted at high-speed data transfer using a single probe head. A periodically inverted signal can be read out correctly with a bit rate of 100 kbps using this test system, and 10 Mbps data transfer is also possible during writing operations. The effect of a dc-offset voltage applied to the writing waveform with high-speed probe scanning is discussed. In addition, a novel noncontact probe height control technique was adopted to solve the problem of tip abrasion.