DC Offset Cancellation Research Articles

A 2.3-5.7 μW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2, and Pulse Transit Time Co-Monitoring.

This paper presents a tri-modal self-adaptive photoplethysmography (PPG) sensor interface IC for concurrently monitoring heart rate, SpO2, and pulse transit time, which is a critical intermediate parameter to derive blood pressure. By implementing a highly-reconfigurable analog front-end (AFE) architecture, flexible signal chain timing control, and flexible dual-LED drivers, this sensor interface provides wide operating space to support various PPG-sensing use cases. A heart-beat-locked-loop (HBLL) scheme is further extended to achieve time-multiplexed dual-input pulse transit time extraction based on two PPG sensors placed at fingertip and chest. A self-adaptive calibration scheme is proposed to automatically match the chip's operating point with the current use case, guaranteeing a sufficient signal-to-noise ratio for the user while consuming minimum system power. This paper proposes a DC offset cancellation (DCOC) approach comprised by a logarithmic transimpedance amplifier and an 8-bit SAR ADC, achieving a measured 38 nA residue error and 8.84 μA maximum input current. Fabricated in a 65nm CMOS process, the proposed tri-modal PPG sensor interface consumes 2.3-5.7 μW AFE power and 1.52 mm2 die area with 102dB (SpO2 mode), 110-116 dB (HR & PTT mode) dynamic range. A SpO2 test case and a HR & PTT test case are both demonstrated in the paper, achieving 18.9 μW and 43.7 μW system power, respectively.

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications.

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is -80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

A Single-Chip Single-Antenna Radar for Remote Vital Sign Monitoring

This article proposes an effective way to use self-injection locking (SIL) in a radar system to detect human chest cavity movement for vital signs monitoring with minimal hardware. The proposed approach expands the idea of using a phase-locked loop (PLL) system as a demodulator and a single antenna, making the system more compact. The system includes on-chip dc offset cancellation for system initialization. This work investigates and compares an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$</tex-math> </inline-formula> -based voltage-controlled oscillator (LCVCO) and a ring voltage-controlled oscillator (RVCO) in terms of primary sensitivity for motion detection and phase noise. A study of injection-locking of both the LCVCO and RVCO is also established. The study shows that the RVCO is superior to the LCVCO in terms of sensitivity while the phase noise does not differ significantly as the frequencies of interest are very small, i.e., heart rate and respiration are bandwidth-limited to a few hertz. To verify the proposed idea, a design of both systems, an LCVCO-based PLL and an RVCO-based PLL, was implemented in 65 nm CMOS technology at 1.5 GHz. The simulation and measurement results confirm the idea proposed: the RVCO shows better performance across all metrics, e.g., higher sensitivity by 4 dB, lower power consumption by 30%, and reduced area (almost half) compared to the LCVCO.

On optimization of Manufacturing Transistors in Wideband Current Amplifier with DC-offset Cancellation to Increase their Integration Rates

On optimization of Manufacturing Transistors in Wideband Current Amplifier with DC-offset Cancellation to Increase their Integration Rates

A Design of Analog Front-End with DBPSK Demodulator for Magnetic Field Wireless Network Sensors

This paper presents an on-chip fully integrated analog front-end (AFE) with a non-coherent digital binary phase-shift keying (DBPSK) demodulator suitable for short-range magnetic field wireless communication applications. The proposed non-coherent DBPSK demodulator is designed based on using comparators to digitize the received differential analog BPSK signal. The DBPSK demodulator does not need any phase-lock loop (PLL) to detect the data and recover the clock. Moreover, the proposed demodulator provides the detected data and the recovered clock simultaneously. Even though previous studies have offered the basic structure of the AFEs, this work tries to amplify and generate the required differential BPSK signal without missing data and clock throughout the AFE, while a low voltage level signal is received at the input of the AFE. A DC-offset cancellation (DCOC), a cascaded variable gain amplifier (VGA), and a single-to-differential (STOD) converter are employed to construct the implemented AFE. The simulation results indicate that the AFE provides a dynamic range of 0 dB to 40 dB power gain with 2 dB resolution. Measurement results show the minimum detectable voltage at the input of AFE is obtained at 20 mV peak-to-peak. The AFE and the proposed DBSPK demodulator are analyzed and fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) technology to recover the maximum data rate of 32 kbps where the carrier frequency is 128 kHz. The implemented DCOC, cascaded VGA, STOD, and the demodulator occupy 0.15 , 0.063 , 0.045 , and 0.03 of area, respectively. The AFE and the demodulator consume 2.9 mA and 0.15 mA of current from an external 5 V power supply, respectively.

An Analog Baseband Circuit for Wireless Local Area Networks Transceiver in 55 nm CMOS Technology

The design of the analog baseband circuit is based on 55 nm CMOS technology and is integrated in an IEEE 802.11ax concurrent dual band four antenna transceiver. A low-pass filter (LPF) of the receiver was multiplexed with an LPF-transmitter such that the last three stages of the fifth order LPF-receiver were used by the LPF-transmitter, and the first programmable gain amplifier (PGA) of the receiver was partially multiplexed with the PGA-transmitter such that the PGA-receiver and the PGA-transmitter shared the same operational amplifier and input resistance, thereby reducing the power consumption, noise, linearity, and area of intermediate frequency (IF) of the transmitter designed separately. The typical bandwidth of the IF-receiver is 10/20/40 MHz; that of the IF-transmitter is 12/24/50 MHz. The gain range of the IF-receiver and the IF-transmitter is 0.1–65.5 dB and −10.1 to 3.98 dB, respectively. Under the voltage of 1.5 V, the current of the IF-receiver is 3.86 mA. As for the IF-transmitter, the current is 1.78 mA when supply voltage is 1.5 V. The input referred noise (IRN) of the IF-receiver at 10 MHz bandwidth (BW) and 62 dB gain is 14.52 nV/√ Hz, while the IRN of the IF-transmitter at 10 MHz BW and −6 dB gain is 95.16 nV/√ Hz. The suppression ability of the DC offset cancellation circuit is 35.08/80.9/110.1/113 dB. The area of the analog baseband circuit is 0.17 mm2.

A 77-dB Dynamic-Range Analog Front-End for Fine-Dust Detection Systems with Dual-Mode Ultra-Low Noise TIA.

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results.

A fast transient RBAOT controlled DC-DC buck converter with dual-loop DC offset cancellation technique and constant switching frequency

A fast transient ripple-based adaptive on-time (RBAOT) controlled DC-DC buck converter is presented in this paper. Firstly, for improving the output DC accuracy while keeping the fast transient response, a dual-loop DC offset cancellation technique is proposed. The fast loop ensures fast transient response, and the slow loop to compensate for the output DC offset introduced by ripple injection. Secondly, considering the parasitic resistances of the devices, the proposed switching frequency compensation technique reduces the frequency variation in steady state regardless of the input output voltage and load current condition. The proposed buck converter has been fabricated using 0.18-μm CMOS process. Measurement results show that the proposed converter has an outstanding output DC accuracy, the output offset is less than 2 mV. Moreover, the switching frequency is centered at 2 MHz with less than 1.5% variation for an output of 1.8 V and inputs ranging from 2.1 to 3.6 V. The maximum conversion efficiency is up to 94.6%, and the transient response times are 2 and 3 μs at rising and falling edges, respectively.

A high speed frontend electronics ASIC for multi-channel single gap RPC detector

This paper presents a high speed prototype frontend electronics (FEE) ASIC, designed to meet the readout requirements of ∼ 3.6 million channels of avalanche mode single-gap resistive plate chamber detectors of Iron Calorimeter experiment of India based Neutrino Observatory. This ASIC is a regulated cascode transimpedance pre-amplifier based octal amplifier-comparator FEE solution in 0.35 μm CMOS process. Two DC stabilization techniques, one for common mode and another for differential DC offset cancellation, have been incorporated in this ASIC to ensure amplifier baseline stability, uniform dynamic range and comparator overdrive across readout channels. This DC common mode control can also be used to trim the input impedance of regulated cascode pre-amplifier. The ASIC provides parallel LVDS outputs on external 100 Ω load for tracking and precision time-tagging. A multiplexed analog output is also provided through an on-chip 50 Ω cable driver for detector pulse profile analysis. The ASIC has total channel gain of ∼ 0.75 mV/fC for single ended inputs of both the polarities, intrinsic timing precision of ∼ 190 ps RMS and ∼ 100 ps RMS for input charge of 0.1 pC and beyond 0.3 pC respectively with total power consumption of 40 mW/channel.

A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS

A low power receiver is designed and implemented for 2.4 GHz Industrial-Scientific-Medical (ISM) band in a 40 nm CMOS process. To obtain good noise and linearity performance at low cost, a current-reused low power inductor-less balun low noise amplifier (LNA) structure is proposed without use of monolithic spiral inductors or transformers. The receiver adopts a zero-IF architecture and current mode mixing operation which avoid need of large voltage headroom for the radio frequency (RF) voltage swing under strong interferers. A third order active-RC low pass filter (LPF) with RC calibration and DC offset cancelation (DCOC) blocks are carefully designed. Current reusing technique and timing optimized asynchronous SAR logic are adopted in LNA and ADC design respectively, featuring high-power efficiency. The total receiver chain achieves maximum conversion gain of 80.32 dB, noise figure (NF) of 6.27 dB and input referred third-order intercept point (IIP3) of −0.6 dBm with 32.8 mW power consumption.

A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring

In this article, we present the design and analysis of a 785-nW multimodal sensor interface IC for ozone pollutant sensing and correlated cardiovascular disease monitoring based on electrocardiography (ECG) and photoplethysmography (PPG). The proposed hybrid dc offset current cancellation (DCOC) along with a 4- MΩ gain-regulated cascode transimpedance amplifier (RGC-TIA) enable PPG readout power reduction by 37×, compared with the state-of-the-art PPG sensor interfaces. The ozone sensing channel proposes an adaptive architecture to enable low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> operation, achieving a 300× power reduction, compared with the state-of-the-art gas sensing readouts. The ozone sensing channel's performance was also verified using custom resistive metal-oxide sensors for concentrations from 50 to 900 ppb. The sensor interface IC is fabricated in a 65-nm CMOS, integrating a 165-nW voltage-mode ECG channel, a 532-nW current-mode PPG channel, 76-nW resistive-mode ozone channel, and 12.6-nW peripheral circuits, all at 0.6 V. The total system power consumption including the LED and a custom digital readout IC is 10.98- 15.51 μW, which is 41×- 57× less than prior ozone/CVD joint monitoring sensor interface systems.

Experimental assessment of Single Phase Grid assisted system using Second Order Generalized Integrator–Frequency Locked Loop

Objectives: To design and develop a simple, robust, and novel SOGI based frequency lock loop approach with DC-offset elimination capability for extracting precise phase angle of the grid voltage. As the additional objective of the work is to utilize the unused capacity of the PV system for providing reactive power support to the grid. Method: The second-order generalized integrator (SOGI)-Frequency Look loop (FLL) is implemented to achieve precise phaseangle for the control system, filtering capability for the adaptive frequency tuning as well as an orthogonal signal generation. The DC blocker is designed to eliminate the dc-offset generated during analog to digital conversion without compromising the dynamics of the system. To achieve the second objective, the virtual two-axis current control is simulated and experimented on in a single-phase grid-assisted system. Synchronous-frame current controllers are designed to inject active power to the grid and also ensure the unity power factor by providing reactive power support to the grid. The developed system is simulated using MATLAB /Simulink and implemented on the experimental stepup. Findings: The precise phase-angle is extracted from the grid voltage during the abnormal grid conditions like frequency shift, distorted by harmonics, and dc-offset. The DC-offset can be eliminated without adopting high-order FLLs by choosing the appropriate control parameter and DC cancellation block (DBC). Novelty: This study presents simple, efficient, novel SOGI based control that provides assurance of power quality as well as injection of active power injection into the grid using the virtual two-axis reference frame power control. The experimental and simulation results confirm that the presented control approach provides fast and accurate phase angle extraction in the grid synchronization with DC-offset cancellation. Keywords: Grid synchronization; STM32F407VG microcontroller; WAIJUNG Blockset; phase detection; Phase Locked Loop (PLL); virtual two axis reference frame power control

A Low Noise 28Gbaud/s Linear PAM4 Receiver Front-End for Optical Communication Applications in 0.13μm BiCMOS Technology

This paper presents a low noise 28 Gbaud/s linear receiver front-end for fourth-order pulse amplitude modulation (PAM4) signal applied in the field of optical communication. The designed receiver front-end includes a transimpedance amplifier(TIA), an automatic gain control (AGC) and a DC offset cancellation (DCOC) circuit. The pseudo-differential structure of the TIA is designed to achieve low noise. The resistance and capacitance degradation technology are introduced in the variable gain amplifier(VGA) and the equalizer(EQ) to improve linearity and optimize the bandwidth. In the AGC mode, the feedback loop controls the output amplitude to be a desired value within a large range of input current. The PAM4 optical receiver front-end achieves a maximum differential transimpedance gain of 76 dBΩ and -3dB bandwidth of 27 GHz. The equivalent input noise current density with the front-end circuit is . In 0.13µm BiCMOS technology, the PAM4 front-end chip consumes 200 mW with a 3.3V voltage supply.

A 25 Gbps single‐end input limiting amplifier with loss of signal for low power integrated optical receivers

AbstractA 25 Gbps limiting amplifier (LA) with loss of signal (LOS) detection is presented in this paper. The proposed LA is composed of an input buffer, three‐stage cascaded amplifier, an output buffer, a DC offset cancellation (DCOC) and a LOS circuit. The LA adopts single‐end input and differential output structure to reduce the complexity of optical receiver front‐end and therefore decrease power consumption drastically. DCOC circuit consists of a low‐pass filter and an operation amplifier to extract the DC point of transimpedance amplifier output signal. Replica peak detector is employed in LOS to overcome the fluctuations of process, voltage, temperature (PVT). Fabricated in 0.13 μm SiGe BiCMOS technology, the LA acquires gain of 43.5, –3 dB bandwidth of 20.6 GHz and differential output voltage swing of 350 mV. With the 20 mV PRBS31 input data, the peak‐to‐peak jitter of output signal is 13.9 ps. When the input swing is larger than 40 mV, the peak‐to‐peak jitter is decreased to 7.5 ps. The whole LA with LOS chip only consumes 25.2 mW with a 1.8 V supply voltage.

A High-Efficiency Fast Transient COT Control DC–DC Buck Converter With Current Reused Current Sensor

This article presents a high-efficiency fast transient constant <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -time (COT) control dc–dc buck converter for the Internet of Things applications. The current reused current sensor is proposed to enhance the loop stability and improve the power conversion efficiency at light load. Input current is sensed and added to the feedback voltage of the dc–dc converter to increase the sensed output ripple voltage. Fast transient dc-offset cancelation technique is introduced to achieve a fast transient recovery time and to cancel the output dc offset. This chip is fabricated with a 0.13- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m CMOS process. A standard supply voltage of 7–15 V is applied to produce the output voltage of 5–5.33 V. The total die area is 2 mm × 1.5 mm. The settling time is 17 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> s. The transient recovery time from light to heavy load and from heavy load to light load are 3 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> s and 2.7 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> s, respectively, with a maximum dc offset of 3.5 mV. The overshoot voltage is 85 mV and the undershoot voltage is 72 mV. The peak efficiency of the proposed design is 95.56% at 0.5 A and efficiency at the light load of 10 mA is 84.60%.

Design and Implementation of a Digital Front-End With Digital Compensation for Low-Complexity 4G Radio Transceivers

A digital front-end with digital compensation is designed and implemented for low-complexity 4G radio transceivers targeted for wearable devices such as smart watches. The proposed digital front-end in the radio receiver consists of an anti-drooping filter, a decimation chain, a DC offset cancellation circuit, and an in-phase and quadrature estimation and compensation circuit whereas the digital front-end in the radio transmitter includes an anti-drooping filter, a root raised cosine filter, and an interpolation chain. The proposed DC offset cancellation circuit is based on both infinite-duration impulse response filter and moving average. The proposed in-phase and quadrature estimation and compensation circuit attains lower complexity with negligible performance loss, compared with an existing circuit. A systematic top-down strategy is taken to design and implement the proposed digital front-end from the algorithm level to the application-specific integrated circuit or ASIC hardware level. The inter-symbol interference in the transmitter and the receiver is analyzed and the unwanted emission in the transmitter is simulated as well. For all the seven bandwidths or modes in 3G and 4G, the digital front end receiver ASIC satisfies all the interference requirements, namely, in-band blocker, narrowband blocker, and adjacent channel selectivity requirements whereas the digital front end transmitter ASIC meets all the unwanted emission requirements, namely, spectrum emission mask, spurious emission, and adjacent channel leakage ratio requirements. The proposed multimode 4G digital front end receiver and transmitter ASICs exhibit a >40dB mean signal-to-noise ratio for all the seven modes and are implemented in a 180nm CMOS process technology.

Bio-Amplifier based on MOS bipolar Pseudo-Resistors: A New Approach using its non-linear characteristic

This paper proposes a new and refined bio-amplifier design, which associates DC offset cancellation, adequate frequency response and buffered outputs to a significant reduction of the signal recovery time. A MOS-Bipolar pseudo-resistor integrated to the feedback network of a single-stage Operational Transconductance Amplifier and the source-follower buffers give to the new topology its main advantages. This architecture makes use of the high resistance values of these pseudo-resistors to eliminate the offset DC level input preserving the low cut-off frequency, without the need of high capacitances, thereby significantly reducing the active die area, which enables its use as a front-end pre-amplifier assembled directly on the acquisition probes. The recovery time after an input voltage transitory of high-amplitude is an important characteristic of the bio-potential amplifiers due to their very low cut-off frequency. The proposed bio-amplifier utilizes the non-linear characteristics of the pseudo-resistor in the recovery time reduction. This time was evaluated and the topology presented a significant contribution in this aspect, assuming values 90% lower when compared with the same topology using a constant resistance. The new amplifier allows voltage gain of 30dB from 0.6 Hz to 2 kHz, and Total Harmonic Distortion (THD) of 0.19% for an input signal of 10Hz. This work also provides a behavioral spice model for MOS-Bipolar pseudo-resistor, which allows an accurate simulation of the linear and nonlinear pseudo-resistor characteristics, obtained through an experimental method of indirect characterization. This method is based on the transitory response from a first order RC low pass filter. The experimental characterization method is of fundamental importance, due to the absence of appropriate SPICE models that describe with precision the pseudo-resistance behavior. The circuits were manufactured by MOSIS on 8HP SiGe BiCmos Global Foundries 0.13μm technology.

A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links

This paper presents the design and measurements of a 25-Gb/s inductorless optical receiver in a 0.25-μm SiGe BiCMOS process for 100-Gb/s (25-Gb/s × 4 lines) Ethernet. As the first stage of the proposed optical receiver, a transimpedance amplifier (TIA) employing a pseudo-differential structure with a feedback resistor incorporates DC offset cancellation (DOC) to enhance the input dynamic range. Cascaded by the improved two-stage limiting amplifiers and a 50-Ω output buffer, the receiver achieves high differential swings. For a bit-error rate (BER) of 10−12 at 25 Gb/s, the measured transimpedance gain, bandwidth, sensitivity, and output swing are 63.17 dBΩ, 20.7 GHz, −10.3 dBm, and 352.7 mV, respectively. The power consumption of the entire receiver is 111.6 mW and the core area of the die is 640 μm × 135 μm.

Modeling and experimental evaluation of pseudo-resistor’s temperature dependence

This work presents the experimental temperature dependence evaluation of the pseudo-resistor piecewise linear (PWL) macromodel, for temperature ranging from 300 to 333 K. The studied macromodel is based on the PWL methodology and it can be used for pseudo-resistors SPICE simulation, including both linear and non-linear operation regions. This study was carried out using a low-frequency bio-potential amplifier with narrow bandwidth for use in QRS complex (part of the electrocardiogram which is a combination of the Q wave, R wave and S wave) detection systems. The architecture based on pseudo-resistors provides DC offset cancellation, adequate frequency response and a significant reduction of the signal recovery time. Both the pseudo-resistor and the QRS complex detector performance were experimentally measured with the temperature variation, in order to include this dependency in the PWL model. The transient recovery time, as well as the QRS complex detector frequency response, was also widely evaluated, in the proposed temperature range, through experimental measurements. The temperature dependence was added to the model and implemented in the SPICE simulation. The model outputs showed strong adherence to experimental data, showing a disagreement less than 6% in the low cut-off frequency. The macromodel’s response to the recovery time also followed the same experimental results behavior, presenting a maximum error of 20% within human body temperature range. The obtained recovery time was less than a normal heartbeat period to the entire temperature range evaluated. All of the analyzed circuits were implemented using GF 8HP 0.13 μm BiCMOS technology from Global Foundries.

A 100-Gbps 4-Lane Transceiver for 47-dB Loss Copper Cable in 28-nm CMOS

A 103.13-Gbps 4-lane transceiver for copper cable applications was fabricated in 28-nm CMOS technology. The transceiver can transmit 103.13-Gbps data through 4-lane 47-dB-loss channels. To achieve this result, ISI should be suppressed; equalization allocation of a four-tap FFE, a CTLE with a low-frequency equalizer and a DFE is optimized with the proposed tap-based auto equalization. In addition, SNR degradation should be suppressed as much as possible to receive a small signal through a large loss channel. Here, a sub-mV dynamic DC offset canceller and a DFE with a bias controlled tap slicer are proposed. The DC offset canceller reduces DC offset of the CTLE to less than 1 mV. The DFE with a bias controlled tap slicer has an input sensitivity finer than 1.2 mV0p, which improves the SNR at the slicer's input and reduces the dead zone of CDR phase detector to less than 1.7 ps. The transceiver consumes 403 mW from a 0.9 V and 1.5 V supply per lane, which includes 1/4 of the power consumption of the PLL and 1/8th the power consumption of the common block.