DC Gain Research Articles

A high current efficiency rail-to-rail operational amplifier

ABSTRACT This paper proposes a new single stage high current efficiency rail to rail amplifier (HCE-RTR). Due to the combination of a new constant transconductance control circuit and local common mode feedback (LCMFB) technique, the proposed rail to rail amplifier not only achieves improvements in unity-gain bandwidth (GBW) and slew rate (SR), but also ensures input stage transconductance constancy within the rail to rail voltage range. Based on the SMIC 180 nm process, the post-layout simulation results show that the proposed amplifier achieves rail-to-rail input/output. The simulated open loop AC response shows the DC gain, GBW, and PM are 66.2 dB, 8.2 MHz, and 60.97 o , respectively. When the driving load capacitance is 70 pF, the transient response simulation results show that the proposed amplifier achieves 0.039 µs average 1% settling time, and about 5.73 V/µs average slew rate. Note that under the condition of 1.8 V power supply, the power consumption is only 122.4 µW, proving the proposed amplifier can achieve high current efficiency while maintaining stability.

Nonisolated Integrated Boost Featured (NIIBF) Multi-Input Ultrahigh Gain DC–DC Converter

Nonisolated Integrated Boost Featured (NIIBF) Multi-Input Ultrahigh Gain DC–DC Converter

A 1.2 V, 92 dB Dynamic-Range Delta-Sigma Modulator Based on an Output Swing-Enhanced Gain-Boost Inverter

This article presents a third-order, feedforward, single-bit Delta-Sigma analog-to-digital modulator (DSM) based on an output swing-enhanced gain-boost inverter for low-voltage low-power applications such as wearable devices, mobile health, and the Internet of Things (IoTs). The proposed output swing-enhanced structure addresses the output-swing reduction in the conventional structure while achieving high DC gain and large output swing simultaneously. Implemented in a 180 nm CMOS process, the entire chip is comprised of a delta-sigma modulator, an oscillator, and a current reference. It achieves 86.1 dB peak SNR and 92 dB dynamic range (DR) with 1.95 kHz signal bandwidth. The whole chip dissipates 54.5 μW, leading to a 167.6 dB Schreier Figure of Merit (FoMs).

Fully real-time configurable analogue implementation of continuous-time transfer function: Application on fractional controller

This paper proposes a new electronic analog circuit to realize real-time fully configurable continuous-time transfer function. The proposed circuit serves various purposes, including smart controllers, fractional-order controllers, optimal controllers, anti-aliasing filter, and programmable filters. The input signal of the transfer function is continuous and remains continuous throughout the circuit until the output signal is obtained. The proposed approach decomposes the transfer function into elementary first and/or second-order low-pass filters. A new analog first-order low-pass filter circuit is presented, offering advantages over conventional active first-order low-pass filters circuits. These benefits include DC gain and time constant independent of resistor ohmic values, enabling the use of smaller resistors and capacitors for low frequencies, and an expanded frequency working range. Similarly, a new analog circuit for a second-order low-pass filter is proposed, specifically used to obtain complex conjugate poles. The use of digital potentiometers and digital switches controlled by a micro-controller, makes this analog circuit configurable in real-time. As an application, the new circuit is used to realize fractional integrator controller. The circuit gives good similarity between theoretical and experimental measurements.

An Extensible Non-isolated Enhanced Gain DC–DC Converter Integrating Switched Capacitor Cell for FCEV

An Extensible Non-isolated Enhanced Gain DC–DC Converter Integrating Switched Capacitor Cell for FCEV

A New High Gain DC–DC Boost Converter Using L-C-L Structure Based Switched Inductor Topology

A New High Gain DC–DC Boost Converter Using L-C-L Structure Based Switched Inductor Topology

Design, Simulation and Comparative Analysis of Two Stage Operational Amplifier Based on CNTFETs Using Indirect Feedback Frequency Compensation

In the course of this study, an efficient implementation of a high gain and low power two-stage operational amplifier using indirect feedback frequency compensation based on CNTFETs. HSPICE software was used to develop and simulate CNTFETs. The op-amps were designed using 0.9[Formula: see text]V input supply voltage. The proposed structures were formed either using CNTFETs only known as pure CNTFET-IFFC-2SOA or hybrid structures consisting a mix of both CNTFETs and conventional CMOS named as PCNTFET-NMOS-IFFC-2SOA and NCNTFET-PMOS-2SOA. The comparative investigation revealed that CNT-based structures performed significantly better than the traditional CMOS-based devices. In the instance of CNTFET-IFFC-2SOA, there was a considerable improvement in DC gain, power dissipation, phase margin, and CMRR. The DC Gain increased by 140.92%, the CMRR increased by 32.94%, and the phase margin increased by 4.9%. Furthermore, at the 32[Formula: see text]nm technology node, a GNRFET-based structure was designed and compared to conventional CMOS and pure CNTFET-based IFFC-2SOA. It was discovered that the DC gain, phase margin, and power dissipation obtained by the CNTFET-based structure were superior to both. The DC Gain of CNTFET-IFFC-2SOA was 156.79% more than that of GNRFET-IFFC-2SOA. To confirm the workability of the proposed circuits, an integrator was designed and simulated as its application. The CNTFET-based IFFC-2SOA integrators showed better integration action than the traditional CMOS-IFFC-2SOA.

Experimental investigation of ANFIS-PSO MPPT control with enriched voltage gain DC–DC converter for grid-tied PV applications

Experimental investigation of ANFIS-PSO MPPT control with enriched voltage gain DC–DC converter for grid-tied PV applications

A linear cross-coupled gate-driven quasi-floating bulk low-power wide input range transconductor.

High linearity for a wider input voltage range and low-power operation of the operational transconductance amplifier (OTA) are indispensable parameters for health care applications, which require high quality and accurate signal conditioning. However, achieving low-power operation along with high linearity at low supply voltages is challenging for OTA using conventional low-power and linearization techniques. This paper proposes an OTA based on a cross-coupled gate-driven quasi-floating bulk (CGDQFB) MOSFET and source-degenerated linearization techniques, which works at a supply of ±0.5V. The post-layout simulations of the proposed OTA are performed in the 180nm standard CMOS process, which shows a transconductance of 0.321 μS, an output impedance of 331 MΩ, an input impedance of 897 GΩ, a DC gain of 40.54 dB, a gain-bandwidth of 0.145MHz, a total harmonic distortion (THD) of 51.09 dB for an input voltage range of 626.7 mV at a frequency of 100.39Hz, and a power consumption of 0.45 μW. The proposed OTA shows an input common mode range of -0.34 to 0.4V, an output voltage swing of -0.34 to 0.34V, a common mode rejection ratio of 91.08 dB, and a consumption area of 23 965.92 µm2. Furthermore, with 200 Monte Carlo iterations, the proposed OTA shows variability for gain and THD of 0.003 and 0.036, respectively. The proposed CGDQFB OTA is a suitable contender for conditioning bio-signals used in health care applications.

Double‐input triple‐output non‐isolated DC–DC converter based on coupled inductor with high step‐up output voltages

SummaryThis paper introduces a new non‐isolated double‐input triple‐output (DITO) high voltage gain DC–DC converter with a wide range of applications, including hybrid voltage source systems, solar home appliances, DC‐bus power distribution systems, and electrical vehicles (EVs). The proposed DITO converter interfaces two hybrid voltage sources to supply three different output loads with varying voltage and power levels. Compared to conventional converters of the same type, the proposed DITO converter offers several advantages, including operation for all duty cycles, integration of hybrid energy sources to transfer power to multiple loads, high voltage conversion ratio for all three‐output ports, a higher ratio of total voltage gain to total components number, common grounded input and output DC ports, simultaneous DC voltage regulation of three‐output ports by tuning separate controlling parameters of duty cycles, an additional turns ratio of coupled inductors to increase the voltage gain of output ports, and medium voltage stress on switches. The proposed DITO converter utilizes a new single‐switch single‐coupled‐inductor DC–DC structure, which is analyzed and verified through a prototype implementation for 25 and 30 V input voltages and 210, 330, and 400 V output voltages with a total power of 480 W. The experimental results confirm the simulation results and theoretical analysis.

A Soft-Switched SEPIC-Based High Voltage Gain DC–DC Converter for Renewable Energy Applications

A Soft-Switched SEPIC-Based High Voltage Gain DC–DC Converter for Renewable Energy Applications

Fully Soft-Switched Single-Switch High Gain DC–DC Topology Based on Coupled Inductor

Fully Soft-Switched Single-Switch High Gain DC–DC Topology Based on Coupled Inductor

An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique

A voltage reference is indispensable in Integrated Circuits. To improve the limited linear output voltage range and energy efficiency of a voltage reference, we innovatively propose a switched-capacitor-based programmable voltage reference scheme employing inverter-based OTAs to reduce the power consumption, simultaneously using a novel Correlated Level Shifting (CLS) technique (without active overhead) to enhance the OTA’s DC gain and integral gain. Experimented with SMIC 180 nm CMOS technology, a scheme-based voltage reference realizes a programable output voltage range from 266 to 995 mV at −30 to 120 °C, and the corresponding temperature coefficient (TC) ranges from 82.4 to 99.5 ppm/°C. The power consumption is 976 nW. Furthermore, comparative experiments and evaluations with other schemes have unequivocally verified the superiority of our proposed scheme, characterized by its high energy efficiency and wide output voltage range. The scheme can be suitably deployed in a multitude of novel edge-data processing systems.

Recycling folded cascode two-stage CMOS amplifier

In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V. The first stage of the circuit utilizes a supper recycling folded cascode design, while the second stage employs a simple cascode amplifier. Additionally, we have utilized a small 1 pF Miller capacitor to stabilize the amplifier response. Based on simulation results, the proposed amplifier demonstrates a DC gain of 110 dB, GBW of 15 MHz, and power consumption of 359 μW. Finally, we conducted Monte Carlo simulations to verify the robustness of the proposed circuit against the process, temperature, supply voltage, and device dimension mismatch variations.

Performance evaluation of a single microchannel plate with large length-to-diameter ratio

The conventional microchannel plate (MCP) detector has found widespread application in various fields. This article focuses on investigating the performance of a single MCP with a large length-to-diameter ratio (L/D) of 80:1, particularly for single electron counting. To enhance MCP performance, alumina with a high secondary electron yield (SEY) is coated onto the MCP using atomic layer deposition (ALD). The SEYs of alumina thin films with different thicknesses are measured using a pulsing electron beam method. The 80:1 L/D MCPs operate in electron counting mode, and the optimal alumina thickness is determined through a comparative study of MCP performance before and after coating. The relationships between maximum SEY, primary electron energy, gain, peak-to-valley ratio (P/V), and pulse height resolution (PHR) are analyzed. After alumina coating, the single 80:1 MCP exhibits improved gain, P/V and PHR. The optimal P/V and PHR of a single MCP as functions of the primary electron energy align with the relationship between the SEY of the alumina coating and the primary electron energy. Additionally, the variation of DC gain with extracted charge is investigated. This article provides valuable insights for parameter selection in achieving the optimal working state of MCP and explores the potential application of single electron counting using a single MCP.

Ultra‐high voltage gain DC–DC converter based on new interleaved switched capacitor inductor for renewable energy systems

SummaryIn this paper, introduces a DC–DC converter design based on a modified hybrid switched inductor‐switched capacitor architecture, aimed at achieving ultra‐high voltage gain in renewable energy systems (RES). The proposed converter involves adding a modified boosting conversion mode (MBM) that interleaves with the main switch to double the voltage transfer gain. Additionally, a modified switched capacitor (MSC) technique, utilizing two diodes as interleaved components, is integrated into the main and auxiliary switches to verify low voltage stress across them. In addition, modified hybrid switched inductors with capacitors (MSIC) and diodes are employed to validate ultra‐high voltage gain. The main advantages of the proposed converter are its high efficiency, low voltage stress across diodes and MOSFETs, and the utilization of low values of inductors and capacitors at high switching frequencies. In addition, the voltage stress across the inductors of the (MSIC) is reduced as the duty cycle increases. Furthermore, the current stress on the main switch is reduced when the charge of capacitor C1 becomes zero. Mathematical models for both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) of the proposed converter are explored. Furthermore, a dual PI controller is designed for the proposed converter to maintain a high fixed output voltage. In addition, the PCB design and experimental testing of the proposed converter to verify the simulation and laboratory results. Specifically, the proposed converter is designed to boost up voltage (30–40 V) to a variable output voltage between 200 and 300 V at 300 W at efficiency 96.7%.

Dual switch ultra-high gain DC–DC converter with low voltage stress

DC microgrids have gained prominence by successfully incorporating renewable energy sources like photovoltaics, fuel cells, etc. through power electronic interfaces. To incorporate renewable energy sources to the DC microgrid, the utilization of DC–DC converters becomes necessary. This requirement arises from the lower voltage levels associated with these energy sources. This paper introduces a new dual switch, ultra-high gain, non-isolated dc–dc converter with low voltage stress. A modified switched inductor(SI) cell is combined with a switched capacitor(SC) cell to obtain a significant gain in voltage for this proposed converter. A second switch is incorporated in lieu of the diode of the SI cell to reduce the voltage stress on the active switches to less than 25% of the output voltage. The reduced voltage stress further contributes to enhancing efficiency while lowering the rating and cost of the components. The experimental findings from a prototype converter rated at 380[V] and 200[W] corroborate the credibility of the proposed methodology. The results also show that the converter has a full-load efficiency of 95.53% and uses its components better.

THE DESIGN OF HIGH EFFICIENCY AND LOW POWER SWITCHED OPAMP

The tendency of design of integrated circuits (ICs) goes to through the power and area reduction way. The surface area of very-large scale integrated circuits is shrinking along with the shrinking of technological dimensions. Power reduction requires usage of low-power design methodologies. The design of Switched-Opamp (SwOp) circuit based on typical Operational Transconductance Amplifier (OTA), with high efficiency is presented. Reduction of power consumption, using digitally controlled switches, is provided. The suggested SwOp was fabricated in a 14nm FinFET technology and achieved a DC gain of 38.4dB, a maximum operating frequency of 11.5GHz and a power consumption of 114.48uW for worst corner (SS) when the load capacitor is 5pF. The power consumption of proposed architecture is reduced about two times. Structure proposed in the paper can be integrated in modern analog-to-digital conversion application, high-speed receivers, memory systems.

A Novel Digital OTA Topology With 66-dB DC Gain and 12.3-kHz Bandwidth

The paper introduces an enhanced digital OTA topology which allows increasing the DC gain thanks to the adoption of an inverter-based output stage. Moreover, a new equivalent small-signal model is proposed which allows to simplify the circuit analysis and paves the way to new frequency compensation strategies. Designed using a 28-nm standard CMOS technology and working at 0.3-V power supply, post-layout simulations show a 66-dB gain and a 12.3-kHz gain bandwidth product while driving a 250-pF capacitive load. As compared to other ultra-low-voltage OTAs in literature, an increase of small and large signal performance, respect to area occupation, equal to 4.6X and 1.5X, respectively, is obtained.

Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications

This manuscript demonstrates the performance comparison of vertically stacked nanosheet FET with various high-k materials in gate stack (GS) configuration. As the high-k dielectric materials are inevitable to continual scaling, in this paper, various high-k dielectric materials such as Si3N4, Al2O3 and HfO2 are incorporated in the GS, and the performance is studied. Further, DC and Analog/RF performance metrics are discussed in detail, and it is noticed that by using HfO2 in high-k GS, the on current (I ON) is enhanced by 46.7% and off current (I OFF) is decreased by 81.6% as compared to conventional NSFET (C-NSFET) without high-k GS. Also, the switching ratio (I ON/I OFF) is increased by 8× from SiO2 to HfO2, ensuring good logic applications. Moreover, compared to the C-NSFET, GS-NSFET with HfO2 offers better values for analog metrics like transconductance (gm) and transconductance generation factor (TGF). However, as the k value increases, the capacitances are also observed to be increased. As a result, the intrinsic delay (τ) increases by 9%, 6% and 20% from SiO2 to Si3N4, Si3N4 to Al2O3, Al2O3 to HfO2, respectively. On top of that, the circuit level demonstration is also performed for resistive load based inverter and ring oscillator (RO) for both C-NSFET GS NSFET with HfO2 as GS material. From circuit analysis, it is observed that by using the GS, the performance of the inverter is increased in terms of noise margins and DC gain. However, the oscillation frequency (f OSC) of 3-stage RO is decreased by 14.7% with the incorporation of GS owing to the increment in gate capacitance (Cgg). Consequently, the results will give deep insights into the performance analysis of NSFET with various high-k materials in gate stack at both device and circuit levels.