Wireless communication for deep-space and satellite applications needs to accommodate the Doppler shift caused by the movement of the space vehicle and should consume low power to conserve the onboard power. A low-power phase-shift keying (PSK) receiver has been designed for such applications. The receiver employs double differential detection to be robust against Doppler shift and uses subsampling with a 1-bit A/D converter and digital decimation architecture at the front end to achieve low-power consumption. The receiver is also designed to be programmable to operate using single-stage differential detection instead of double-stage differential detection at low Doppler rates to obtain optimum performance. Furthermore, the baseband can be employed in either direct subsampling or intermediate frequency (IF)-sampling front ends. Both front ends offer minimal power consumption and differ from traditional types by replacing some conventional analog components such as a voltage-controlled oscillator, mixer, or phase-locked loop with their digital counterparts. This eliminates problems due to dc offset, dc voltage drifts, and low-frequency (LF) noise. The paper also includes a brief discussion of the nonidealities existing in real applications. The proposed phase shift keying (PSK) receiver supports a wide range of data rates from 0.1-100 Kbps and has been implemented in a CMOS process.