DC Performance Of Devices Research Articles

DC/RF performance and temperature sensitivity of ground-plane based JLTFET

ABSTRACT This paper analyses the effect of temperature variations on the device performance of a ground plane junctionless tunnel field effect transistor (GP-JLTFET) with a high-K gate stack. Ground plane screens the electric field at the drain interface, which results in a higher effective channel length. This leads to highly suppressed ambipolarity and enhancement of the drive current. The junctionless device structure reduces the complexity of high-temperature doping processes as well. As high- gate oxide and metal gate are incorporated, this also aids in increasing the gate controllability and reduced leakage. As the tunnelling mechanism is temperature-dependent, hence, for investigating the feasibility of device application at elevated temperature, these temperature variation effects need to be analysed in depth. The primary goal of this investigation is to analyse the device dc performance parameters like drain current characteristics and subthreshold slope (SS), threshold voltage (), and ratio. Furthermore, the impact of temperature on analogue/RF figures of merit has also been analysed in detail here.

Impact of the mole fraction modulation on the RF/DC performance of GaAs1−xSbx FinFET

AbstractThe impact of mole fraction variation on the RF/DC performance of GaAs1−xSbx‐based FinFET has been examined in this study. Changing the Sb mole fraction has substantial effect on the electronic band parameters of GaAs, which directly affects the device performance. Electrical properties of the device including electron density and mobility fluctuation are investigated as a function of Sb mole fraction. Additionally, device DC performance parameters such as the ION/IOFF ratio, threshold voltage, transconductance, and device node capacitance, such as Cgg and Cds, are studied using a technology computer‐aided design (TCAD) simulator. The mole fraction dependence of the gate capacitance dictates the application of the proposed FinFET in the RF and high‐frequency domains. A detailed investigation of the figures of merits such as intrinsic gain, intrinsic delay, dynamic power dissipation, power delay product, energy dissipation, and unity gain bandwidth reveals that GaAsSb can be a potential material for realization of low‐power analog and digital circuits. The proper tuning of the mole fraction can help to optimize the device performance.

Optimization of Si-doped HfO2 ferroelectric material-based negative capacitance junctionless TFET: Impact of temperature on RF/linearity performance

This paper addresses the effect of temperature variation on the performance of a novel device structure Si-doped Hf[Formula: see text] negative capacitance junctionless tunnel field effect transistor (Si:Hf[Formula: see text] NC-JLTFET). Here, Si:Hf[Formula: see text] ferroelectric material is deployed as gate stack along with high-K gate dielectric Hf[Formula: see text]. Si:Hf[Formula: see text] ferroelectric material generates NC effect during the device operation. This phenomenon is an effective technique for intrinsic voltage amplification, reduction in power supply, as well as minimization of power dissipation. The proposed device structure has two variants, symmetric and asymmetric with respect to the oxide thickness between electrode and Si body at both drain and source sides. As band-to-band tunneling in TFET is temperature dependent, it is very crucial to analyze the impact of temperature variation on the device performance. This work is mainly focused on investigating the device dc performance parameters, analog/RF performance parameters and linearity performance parameters by observing the impact of temperature variation. The device characteristics reveal that for dc and RF performance parameters, asymmetric structure shows better result. Highest [Formula: see text] ratio and minimum SS are reported as [Formula: see text] and 20.038 mV/dec, respectively, at 300K for asymmetric structure. At elevated temperatures higher cutoff frequency and reduced intrinsic delay project the device as a strong candidate for ultra low-power and high switching speed applications. Further, the reported device shows better linearity performance at higher temperatures.

Unraveling Structure and Device Operation of Organic Permeable Base Transistors

AbstractOrganic permeable base transistors (OPBTs) are of great interest for flexible electronic circuits, as they offer very large on‐current density and a record‐high transition frequency. They rely on a vertical device architecture with current transport through native pinholes in a central base electrode. This study investigates the impact of pinhole density and pinhole diameter on the DC device performance in OPBTs based on experimental data and TCAD simulation results. A pinhole density of NPin = 54 µm−2 and pinhole diameters around LPin = 15 nm are found in the devices. Simulations show that a variation of pinhole diameter and density around these numbers has only a minor impact on the DC device characteristics. A variation of the pinhole diameter and density by up to 100% lead to a deviation of less than 4% in threshold voltage, on/off current ratio, and sub‐threshold slope. Hence, the fabrication of OPBTs with reliable device characteristics is possible regardless of statistical deviations in thin film formation.

III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications

Abstract This article presents a comparative study on the performance characteristics of some vertical tunnel field effect transistor (TFET): conventional all-Si TFET with pocket, In0.53Ga0.47As/Si heterojunction TFET with pocket and GaSb/Si heterojunction TFET with pocket. Low band gap materials like In0.53Ga0.47As and GaSb are used here in source region of the TFETs which reduces the tunnel width to cause a greater number of carriers to tunnel through the source-channel heterojunction. Proposed III-V/Si heterojunction TFETs offer better sub-threshold swing, ION/IOFF ratio and lower threshold voltage over the conventional all-Si vertical TFET with pocket at VDS = 0.5 V. Along with the DC parameters, different analog/RF parameters are also extensively studied for all three TFET devices. In addition to this, effect of temperature on device DC performance is thoroughly investigated for the presented TFETs. Linearity parameters are also studied for all the three devices to assure better performance in a communication system at high-frequency.

An improved large signal model of InP HEMTs * * Project supported by the National Natural Science Foundation of China (No. 61331006).

An improved large signal model for InP HEMTs is proposed in this paper. The channel current and charge model equations are constructed based on the Angelov model equations. Both the equations for channel current and gate charge models were all continuous and high order drivable, and the proposed gate charge model satisfied the charge conservation. For the strong leakage induced barrier reduction effect of InP HEMTs, the Angelov current model equations are improved. The channel current model could fit DC performance of devices. A 2 × 25 μm × 70 nm InP HEMT device is used to demonstrate the extraction and validation of the model, in which the model has predicted the DC I–V, C–V and bias related S parameters accurately.

SiC BJT Compact DC Model With Continuous- Temperature Scalability From 300 to 773 K

The first vertical bipolar intercompany (VBIC)-based compact dc model has been developed and verified for a low-voltage 4H-SiC bipolar junction transistor to continuously map a wide temperature range from 300 to 773 K. Temperature and doping dependent physical models for bandgap, incomplete ionization, carrier mobility, and lifetime have been taken into account to give physically meaningful fitting parameters for the compact model. Isothermal simulations using the default VBIC model are performed to extract key parameter sets from measured data at seven different temperature points. Then new temperature dependent equations for the key parameters are proposed and embedded in the default VBIC model. Consequently, a single set of model parameters at 300 K is used to achieve fitting over a wide temperature range from 300 to 773 K. This new model can be used for simulating circuits that require continuous description of device dc performance over a wide temperature range.

Study of the Effects of GaN Buffer Layer Quality on the dc Characteristics of AlGaN/GaN High Electron Mobility Transistors

AlGaN/GaN high electron mobility transistors (HEMTs) are promising candidates for high power and high current applications with its high mobility and high breakdown field. Epitaxial films for device substrate are typically grown on sapphire or silicon carbide, SiC, with dislocation densities in the order of 108 - 1010cm-2 due to their thermal coefficient and lattice mismatches. The thinner GaN buffer layers on SiC have been reported to have higher threading dislocation density in the GaN, but lead to higher off-state breakdown voltages. However, thick GaN buffer layers on sapphire and their impact on dc performance have not been widely studied. In this study, the impact of GaN buffer layer quality on dc and gate-lag pulse performance of AlGaN/GaN HEMTs was studied. Transmission electron microscopy (TEM) was used to measure the dislocation density in the GaN buffer layer of the HEMT samples. Dc characteristics, including drain I-Vs, transfer characteristics, and gate pulsed drain I-V characteristics of the HEMTs, were measured to establish a correlation between the AlGaN/GaN HEMTs’ dc and gate-pulsed performance and GaN buffer layer quality. AlGaN/GaN HEMT structures grown by metal organic chemical vapor deposition (MOCVD) on sapphire substrates were acquired from two different vendors. Both types of wafers had 24% Al concentration in the AlGaN barrier layer. One type of wafer had a 5 µm GaN buffer and the other had a 2 µm GaN buffer layer. HEMT fabrication was started with mesa patterning by conventional optical lithography. The mesa-etching was achieved using a unaxis shuttle-lock reactive ion etcher with inductively coupled plasma module (ICP) for device isolation with a Cl2/Ar plasma. Ohmic metallization of electron-beam evaporated Ti/Al/Ni/Au (25 nm/125 nm/45 nm/100 nm) was patterned by lift-off and subsequently rapid thermally annealed at 850⁰C in a flowing N2 ambient for 45 seconds. Schottky gates of e-beam evaporated Ni/Au (20 nm/80 nm) with 100 μm width and 1 μm length were obtained by standard lift-off patterning. DC current–voltage (I-V) characteristics were measured using an HP4156 parameter analyzer, and gate-lag pulse measurements were measured using an Agilent 8114A pulse generator. Figure 1 shows the bright field cross-sectional transmission electron microscopy (BF-XTEM) pictures of AlGaN/GaN surface for the top layers of (a) HEMT structure with 2 µm GaN buffer layer, (b) HEMT structure with 5 μm GaN buffer layer as well as the GaN/sapphire interface for the (c) HEMT structure with 2 μm GaN buffer layer, and (d) HEMT structure with 5 μm GaN buffer layer. Dislocations are seen to originate near the GaN/sapphire interface and propagate up through the AlGaN/GaN interface to the surface of both HEMT wafers. However, it is clear that the HEMT structure with 2 μm GaN buffer layer exhibited a much higher defect density. The calculated defect density for 2 μm GaN buffer layer substrate had an order of magnitude higher defect density. However, 5μm GaN buffer layer wafer showed that it was under high strain with larger height difference across the 2 inch with lower radius of curvature. There was no major difference in HEMTs’ dc performance was observed. In the other hand, Figure 2 (a) and (b) shows that gate lag measurement on fabricated HEMTs on 5 μm GaN buffer layer wafer showed no degradation and on 2 μm GaN buffer layer wafer showed the otherwise. The effects of defect density on HEMT dc and radio frequency performance were studied. HEMTs were fabricated on 2 and 5 μm of GaN buffer layers with the same composition of active layers. Despite there was no significant difference was seen in dc characteristics, significant reduction in pulse measurements was observed on thinner GaN layer HEMTs. These results suggest that the defects created in GaN buffer layer do not largely influence device dc performance but are closely related to high frequency performance. Figure 1

Investigating the Effects of Annealing on Off-State Step-Stressed AlGaN/GaN High Electron Mobility Transistors

AlGaN/GaN High Electron Mobility Transistors (HEMTs) have shown great promises for high frequency and high power applications. However, there remain some undesired issues such as electron trapping at surface states of AlGaN/GaN HEMTs, which affect the breakdown voltage, gate leakage current and current collapse. These issues hamper the advancement of AlGaN/GaN high power and high frequency device technology and have not been fully understood. Therefore, understanding and control of trap-related effects is very important to improve the performance of AlGaN/GaN HEMTs. Recently, post-process annealing has been widely employed to increase the performance of AlGaN/GaN HEMTs. In this work, the effects of annealing on off-state drain-voltage step-stressed AlGaN/GaN HEMT dc performance, pulsed characteristics and trap densities will be investigated. AlGaN/GaN HEMT heterostructures were grown on semi-conducting 6H-SiC substrates. The epi-layers consisted of a thin AlN nucleation layer, 2.25 μm of Fe-doped GaN buffer, 15 nm of Al0.28 Ga0.72N, and a 3nm undoped GaN cap. The HEMTs employed dry etched mesa isolation, Ti/Al/Ni/Au Ohmic contacts alloyed at 850 °C, and dual-finger Ni/Au gates patterned by lift-off. The gate length was 1µm, and gate width was 2×150 µm. Both source-to-gate gap and gate-to-drain distances were 2 µm. The drain step-stress condition were set for holding 60 seconds at each drain voltage step, while grounding the source electrodes and maintaining as VG = -8V. The stress started at VDS = +5V, and the voltage step was +1V. Annealing was conducted for 10 min at 450 °C under a N2 atmosphere using a Steag 100CS rapid thermal annealing system. An automated temperature control chuck from Wentworth was used to perform temperature dependent measurements. The base temperature was varied from room temperature to 300 °C and held constant during the measurement. The device dc characteristics were measured with a HP 4156 parameter analyzer. It was reported by several groups that gate metal diffusion and notches formed on the AlGaN/GaN layer along the gate edges on both source and drain sides [1,2]. These defects were suggested to be the causes of permanent device degradations for lowering drain current on/off ratio and saturation drain current as well as increasing reverse bias gate leakage current. However, with a 10 min annealing in nitrogen ambient at 450°C, the degradations of drain current on/off ratio, gate leakage and saturation current recovered, as illustrated in Figure 1. Thermal annealing process will not reverse the gate metal diffusion nor alleviate notch formation on the AlGaN/GaN layer. Since the annealing can recuperate the dc performance, the degradations of HEMT dc performance after off-state drain-voltage step-stress are not related to the gate metal diffusion nor the notch formation on the AlGaN/GaN layer. Post-processing annealing at around 400-450°C has been suggested to enhance device dc performance in terms of lowering gate leakage current and enhancing drain saturation current [3,4]. It was suggested that thermal annealing could remove shallow traps. Temperature-dependent sub-threshold swing analyses were conducted to extract trap density, as shown in Figure 2 . The trap density increased from 4.66 × 1012 /cm2-V to 1.04 × 1013 /cm2-V after off-state step-stress and recued to 7.3 × 1012 /cm2-V after 450°C annealing. In conclusion, the new degradation mechanism of dc performance for off-state drain-voltage step stressed AlGaN/GaN HEMT was proposed. Shallow traps were responsible for the degradation instead of gate metal diffusion or notch formation on AlGaN/GaN layer along the gate edges and the device degradation can be removed with a 450°C annealing. Reference: Lu Liu, Tsung Sheng Kang, David A. Cullen, Lin Zhou, Jinhyung Kim, Chih-Yang Chang, Erica A. Douglas, Soohwan Jang, David. J. Smith, S. J. Pearton, Wayne J. Johnson and Fan Ren, J. Vac. Sci. Technol. B 29, 032204-1-5 (2011).P. Makaram, J. Joh, J. A. del Alamo, T. Palacios, and C. V. Thompson, Appl. Phys. Lett. 96, 233509 (2010).Lu Liu, Yuyin Xi, Shihyun Ahn, and Fan Ren, Brent P. Gila, Stephen J. Pearton, Ivan I. Kravchenko, J. Vac. Sci. Technol. B 32, 052201-1-5 (2014).Ronghua Wang, Paul Saunier, Yong Tang, Tian Fang, Xiang Gao, Shiping Guo, Gregory Snider, Patrick Fay, Debdeep Jena, and Huili Xing, IEEE Electr Device L. 32, 309 (2011). Figure 1

Effect of Gamma Irradiation on DC Performance of Circular-Shaped AlGaN/GaN High Electron Mobility Transistors

AlGaN/GaN High Electron Mobility Transistors (HEMTs) show great promise for applications such as military radar and satellite-based communications systems. Due to the applications in extreme radiation environments, it is important to characterize the performance after irradiation. There are many studies characterizing the performance under proton, neutron, and electron irradiations for AlGaN/GaN HEMTs. However, the studies for gamma irradiation are limited. Detailed studies are needed to characterize the performance of HEMTs after gamma irradiation. In this study, we characterize the DC performance after irradiation and extract the change of Vth, carrier concentration, mobility and resistance. Also, we use gate lag measurement and drain pulse measurement to characterize the defects generated after irradiation. AlGaN/GaN HEMT heterostructures were grown on c-plane sapphire by molecular beam epitaxy (MBE). The layer structure included a thin AlGaN nucleation layer followed with a 2 µm thick undoped GaN buffer topped by a 25 nm thick unintentionally doped Al0.28GaN layer. Mesa isolation was achieved by using an inductively coupled plasma system with Ar/Cl2-based discharges. The Ohmic contacts were formed by lifting-off e-beam evaporated Ti (200 Å)/Al (1000 Å)/Ni (400 Å)/Au (800 Å). 1-µm gates were defined by lift-off of e-beam deposited Ni/Au metallization. The contacts were annealed at 850°C for 45 s under a flowing nitrogen ambient in Heatpulse 610T system. The final step was deposition of e-beam evaporated Ti/Au (300 Å/1200 Å) interconnection contacts. Devices were exposed to 60Co γ-rays with different doses of 50, 300, 450, or 700 Gy. Irradiations were performed at temperatures <50°C. During device irradiation, the samples were held in nitrogen ambient. The device DC performance was characterized using HP 4156 parameter analyzer.As shown in Figure 1, IDSS after irradiation was increased from 293mA/mm to 339mA/mm after irradiation. The increase of IDSSincreases with dose before 450 Gy and saturates after that. From the transmission line method (TLM), there is no significant change in sheet resistance after irradiation. However, the device total resistance, the reciprocal of the current current voltage (I-V) curve slope in the lower drain bias voltage, decreased significantly, as illustrated in Figure 1. The total resistance consisted of the channel resistance and the source resistance as well as the drain resistance. Both The source resistance and the drain resistance determined from the transmission line method change less than 2%. While the channel resistance decreased around 5% as shown in Figure 2. The reduction of the channel resistance was mainly due to the increase of mobility and carrier concentration, which were extracted from the drain IV curve in the low field region and TLM data. Kurakin et. al 1 found a similar effect that mobility increases after irradiation due to the relaxation of strain. Berthet et. al 2 attributed the drain current increases after irradiation to the introduction of donor type defects through the implantation. From gate lag measurement, the dispersion of the drain current measured at 100kHz increased as a function of the gamma irradiation dose indicating additional traps generated between gate and drain electrode and enhanced the current collapse. There was no obvious current dispersion during the drain pulse measurement showing the defects created by the gamma irradiation were less than the original defects through the material growth in the buffer layer.In conclusion, low dose gamma irradiation improved the AlGaN/GaN HEMT dc performance. The effect may be due to the strain relaxation effect and due to the donor type defects generated during the gamma irradiation.

Effect of Proton Irradiation on DC Performance and Reliability of Circular-Shaped AlGaN/GaN High Electron Mobility Transistors

AlGaN/GaN High Electron Mobility Transistors (HEMTs) show great promise for applications such as military radar and satellite-based communications systems. Circular devices, with smaller junction areas and higher effective gate width/gate length, are better suited for high power, high frequency application. Since the circular devices have been shown to improve the device performance, the effect of radiation on their reliability is an important topic. There are many studies characterizing the performance under proton, neutron, and electron irradiations for rectangular AlGaN/GaN HEMTs. However, the studies for circular-shaped devices are limited. In this work, we report the effect of proton irradiation on circular-based AlGaN/GaN HEMT. DC performance, breakdown voltage, and gate lag measurement were done to characterize the devices.AlGaN/GaN HEMT heterostructures were grown on c-plane sapphire by molecular beam epitaxy (MBE). The layer structure included a thin AlGaN nucleation layer followed with a 2 µm thick undoped GaN buffer topped by a 25 nm thick unintentionally doped Al0.28GaN layer. Mesa isolation was achieved by using an inductively coupled plasma system with Ar/Cl2-based discharges. The Ohmic contacts were formed by lifting-off e-beam evaporated Ti (200 Å)/Al (1000 Å)/Ni (400 Å)/Au (800 Å). Gates with the dimension of 1.5 µm × 314 µm were defined by lift-off of e-beam deposited Ni/Au metallization. The contacts were annealed at 850°C for 45 s under a flowing N2 ambient in Heatpulse 610T system. The final step was deposition of e-beam evaporated Ti/Au (300 Å/1200 Å) interconnection contacts. Devices were exposed to protons with 5 MeV and different doses of 2×1014 proton/cm2. The device DC performance was characterized using an HP 4156 parameter analyzer. The breakdown voltage was conducted with a Tektronix 370A curve tracer. FLOODS TCAD finite-element solver was used to simulate the electrical field around the gate edge to confirm the experimental result.As shown in Figure 1, drain current IVs, IDSS, decreased from 454 to 398 mA/mm after irradiation with a proton dose of 2×1014 cm-2. Moreover, resistance between source and drain increased and extrinsic transconductance decreased after irradiation. However, the drain breakdown voltage increased from 150 to 230 V. The improvement of the breakdown voltage was due to the reduction of electric field at the edge of the gate, caused by the defects generated by proton irradiation at AlGaN/GaN interface, which was confirmed with simulation, as shown in Figure 2.Both gate and drain pulse measurements were also performed to verify the introductions of implanted defects into the HMET structure, which will be discussed in the talk.

Dependence of Hot Carrier Reliability and Low Frequency Noise on Channel Stress in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

In this paper, the dependence of low-frequency (LF) noise, such as 1/f noise and random telegraph signal (RTS) noise, and the hot carrier reliability in n-channel metal–oxide–semiconductor field-effect transistors (NMOSFETs) on channel stress has been studied. The normalized noise power spectral density (SID /ID2) and RTS amplitude of NMOSFETs with compressive channel stress are greater than those with tensile channel stress because the active traps contributing to RTS noise with compressive stress are distributed closer to the Si/SiO2 interface. LF noise characteristics, as well as device performance are enhanced by introducing tensile channel stress to nanoscale NMOSFETs. However, it is shown that device degradation caused by tensile channel stress is greater than that caused by compressive channel stress under channel hot carrier (CHC) and drain avalanche hot carrier (DAHC) stress conditions. Therefore, concurrent consideration of reliability and LF noise characteristics as well as dc device performance is necessary in channel strain engineering for next generation complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) especially for analog or mixed signal integrated circuit applications.

Dependence of Hot Carrier Reliability and Low Frequency Noise on Channel Stress in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

In this paper, the dependence of low-frequency (LF) noise, such as 1/f noise and random telegraph signal (RTS) noise, and the hot carrier reliability in n-channel metal–oxide–semiconductor field-effect transistors (NMOSFETs) on channel stress has been studied. The normalized noise power spectral density (SID/ID2) and RTS amplitude of NMOSFETs with compressive channel stress are greater than those with tensile channel stress because the active traps contributing to RTS noise with compressive stress are distributed closer to the Si/SiO2 interface. LF noise characteristics, as well as device performance are enhanced by introducing tensile channel stress to nanoscale NMOSFETs. However, it is shown that device degradation caused by tensile channel stress is greater than that caused by compressive channel stress under channel hot carrier (CHC) and drain avalanche hot carrier (DAHC) stress conditions. Therefore, concurrent consideration of reliability and LF noise characteristics as well as dc device performance is necessary in channel strain engineering for next generation complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) especially for analog or mixed signal integrated circuit applications.

New Observation of Mobility and Reliability Dependence on Mechanical Film Stress in Strained Silicon CMOSFETs

This paper shows that dc device performance and reliability characteristics of CMOSFETs do not have the same dependence on the film stress of contact etch stopping layers (CESLs) in strained silicon technology. Two kinds of CESLs, namely, plasma-enhanced chemical vapor deposition (PE-CVD) SiN and low-pressure CVD SiON, with tensile and compressive stresses, respectively, were used to induce channel stress. To further analyze the effects of stress, the film stress of PE-CVD SiN was intentionally split into compressive stress and tensile stress. It is shown that the initial Dit of NMOS with a tensile stress film is less than that with a compressive stress, whereas in the case of PMOS, compressive stress demonstrated less Dit than the tensile-stress film. However, device degradation by hot and cold carriers is heightened more by tensile stress than by compressive stress for both NMOS and PMOS. Therefore, the compressive stress is desirable to improve hot-carrier immunity in NMOSFETs, whereas the tensile stress is necessary to improve the dc device performance. Hence, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs.

Full band Monte Carlo simulation of dislocation effects on 250 nm AlGaN-GaN HEMT

In this work, we present a full band Monte Carlo simulation of the effects of dislocation scattering on the performance of a 0.25 μm AlGaN/GaN HEMT (high electron mobility transistor). We performed a full characterization of the device and validated the simulation results with experimental data (Lee et al. in IEEE Electron. Dev. Lett. 24:613–615, [2003]). Here we show a study of the DC device performance as a function of the density of thread dislocations.

Analysis of DC characteristics of GaAs double heterojunction bipolar transistors (DHBTs) with a pseudomorphic GaAsSb base

In this paper, DC characteristics in GaAs DHBTs with pseudomorphic GaAsSb base layer are investigated using an analytical approach. Devices using different GaAs1−xSbx base thickness with different Sb compositions were simulated to gain an in-depth understanding on the effect of base layer design on the device DC performance. Our calculated results show that, in the GaAsSb base with high Sb composition, the strain plays a non-negligible role in determining the overall device performance. The reduction of B–E turn-on voltage using a large Sb composition of GaAs1−xSbx could be partially compensated by strain in the base. Furthermore, for the devices using high Sb composition, a thin base layer has to be used to ensure elastic strain. In order to maintain reasonable base conductivity that is critical for device microwave performance, high base doping is required. However, our simulation reveals a drastic reduction of DC gain with the increase in base doping, while a high emitter doping may be helpful for the compensation of the degradation of β. A proper design of the device structure by taking the aforementioned issues into account is important for improving device DC and microwave performance.

Effect of thin emitter set-back layer on GaAs delta-doped emitter bipolar junction transistor

GaAs delta-doped emitter bipolar junction transistors (δ-BJT) with different emitter set-back layer thicknesses of 10to50nm were fabricated to study the emitter set-back layer thickness effect on device dc performance. We found that the current gain decreases following decrease in the emitter set-back layer thickness. A detailed analysis was performed to explain this phenomenon, which is believed to be caused by reduction of the effective barrier height in the δ-BJT. This is due to change in the electric-field distribution in the delta-doped structure caused by the built-in potential of the base-emitter (B-E) junction. Considering the recombination and barrier height reduction effects, the thickness of the emitter set-back layer should be designed according to the B-E junction depletion width with a tolerance of ±5nm. The dc performance of a δ-BJT designed based on this criteria is compared to that of a Al0.25Ga0.75As∕GaAs heterojunction bipolar transistor (HBT). Both devices employed base doping of 2×1019cm−3 and base-to-emitter doping ratio of 40. Large emitter area (AE≈1.6×10−5cm−2) and small emitter area (AE≈1.35×10−6cm−2) device current gains of 40 and 20, respectively, were obtained in both types of transistors passivated by (NH4)2S treatment. The measured current gain of the GaAs δ-BJT is the highest reported for a homojunction device with such high base-to-emitter doping ratio normally used in HBT devices.

Regrown-emitter InP heterojunction bisucpolar transistors

We present the molecular beam epidaxy (MBE) growth and the dc device performance of the first fully epitaxial regrown-emitter InP heterojunction bipolar transistors (HBTs). Here the emitter layers are regrown by MBE onto a patterned base–collector template. This process is aimed at reducing the emitter resistance, a key parameter for scaling high speed logic circuits. Emitter resistance is reduced because the emitter contact is formed to an extrinsic emitter larger than the base–emitter junction. Scanning electron microscope images demonstrate controlled, uniform etching to the intrinsic base layer, high-quality epitaxial MBE growth onto the patterned surface, and good sidewall coverage. HBTs with base-emitter junctions ranging from 48×48 to 2.5×2.5μm2 have maximum dc current gains between 5.0 and 7.5. Comparison to regular HBTs shows that the dc current gains are limited by excess base currents. Possible contributions to the excess base currents are discussed. Transmission line method measurements show t...

Annealing temperature stability of Ir and Ni-based Ohmic contacts on AlGaN∕GaN high electron mobility transistors

Ti ∕ Al ∕ Ir ∕ Au Ohmic contacts on AlGaN∕GaN high electron mobility transistors (HEMTs) show promising electrical performance, with lower specific contact resistance than obtained with the more conventional Ti∕Al∕Ni∕Au metallization. HEMTs with both types of metallization have been measured up to 550°C. We find that the dc performance of devices with Ir-based contacts is significantly better at each temperature up to this maximum value, with higher transconductance (gm), saturated drain-source current (IDSS), and more stable threshold voltage (Vth). These contacts look very promising for HEMT power amplifier applications involving high temperature operation.

A model for the dc electrical behavior of bulk-barrier diodes

This paper presents an analytical model for the dc electrical behavior of bulk barrier diodes (BBD's). The proposed model extends previously published models, and includes analytical expressions for all significant quantities of the device dc performance, i.e. barrier height, current density and ideality factor, with respect to the technological parameters and the applied voltage in both bias conditions. The analytical results have been compared with those obtained using the 2-D device simulator S-PISCES, which takes into account the drift–diffusion theory, as well as a concentration and field dependent mobility, the Shockley–Read–Hall and Auger carrier recombination, and the band gab narrowing. Good agreement was obtained between theory and simulation. The device simulation played a very important role in best understanding BBD's behavior, because it could easily take into account parameters strongly affecting the behavior of BBD's, e.g. the free carrier presence in depletion layers, which was very difficult for the analytical model to include.