Requirement of large number of levels with lower number of switching devices has made asymmetrical converters more popular than the symmetrical ones. Asymmetrical cascaded multilevel inverters (ACMLI) can achieve high efficiency by combining switching devices with different voltage ratings and technologies. The proposed ACMLI cascades two or more units of packed U-Cell (PUC) inverters using two or more isolated dc link supplies. In this article, one of the PUC unit is controlled using high switching frequency while the other PUCs are operated in a step mode at low switching frequencies, thus operating them in a variable frequency control mode. The cascading of two 7-level PUC inverters with dc link voltage ratio of 1:7 can produce an output voltage with 49 (7x7) levels. The multilevel output voltage waveform is nearly sinusoidal with very low THD content, and the low switching frequency operation leads to lower power dissipation and greater system efficiency. However, each PUC module requires two dc voltage sources. To address this concern, in this article, each PUC module consists of one dc voltage source and one dc bus capacitor. With the cascaded PUC topology and proposed control algorithm, load current and dc bus capacitor voltage control is achieved simultaneously. The proposed converter and its control technique lead to the breaking of the design tradeoff rule between switching frequency (efficiency) and filter size. This is very useful in various applications such as uninterruptible power supplies and grid-tie inverters. The converter and its control technique are simulated using MATLAB/Simulink software and simulation results for both open loop and closed loop are discussed. Hardware results are obtained by developing a 1-kW experimental prototype. Simulation and experimental results confirm the usefulness and effectiveness of the proposed topology and its control technique.
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