dBm Peak Output Power Research Articles

A 77 GHz Power Amplifier with 19.1 dBm Peak Output Power in 130 nm SiGe Process.

This article reports a two-stage differential structure power amplifier based on a 130 nm SiGe process operating at 77 GHz. By introducing a tunable capacitor for amplitude and phase balance at the center tap of the secondary coil of the traditional Marchand balun, the balun achieves amplitude imbalance less than 0.5 dB and phase imbalance less than 1 degree within the operating frequency range of 70-85 GHz, which enables the power amplifier to exhibit comparable output power over a wide operating frequency band. The power amplifier, based on a designed 3-bit digital analog convertor (DAC)-controlled base bias current source, exhibits small signal gain fluctuation of less than 5 dB and saturation output power fluctuation of less than 2 dB near the 80 GHz frequency point when the ambient temperature varies in the range of -40 °C to 125 °C. Benefiting from the aforementioned design, the tested single-path differential power amplifier exhibits a small signal gain exceeding 16 dB, a saturation output power exceeding 18 dBm, and a peak saturation output power of 19.1 dBm in the frequency band of 70-85 GHz.

Triple-Mode Reciprocal Doherty Power Amplifier With Multi-Band Operation and Extended High Efficiency Range

This article presents the methodology for designing triple-mode Doherty power amplifier (DPA) with multi-band operation and extended high efficiency range. It is illustrated that three different Doherty operation modes can be realized by simply re-setting the gate bias voltages while the DPA circuits keep unchanged. By employing a novel reciprocal gate bias DPA architecture, five operation bands have been achieved by the proposed DPA with larger than 9 dB high efficiency power range. The active load modulation process and theoretical performance of proposed DPA are analyzed in detail for each mode. For verification, a commercial GaN transistors-based DPA is designed and implemented with 1.76-1.96 GHz band in Mode I, 1.13-1.20/2.48-2.58 GHz bands in Mode II and 0.7-0.76/2.34-2.40 GHz bands in Mode III. The fabricated DPA achieves 7.0-10.5 dB saturation gain, 44.18-46.86 dBm peak output power and 41.9%-61.5% back-off efficiency. When stimulated by a 10 MHz long term evolution (LTE) modulation signal with 8.6 dB peaking-to-average ratio (PAPR), the adjacent channel power ratio (ACPR) of the fabricated DPA is better than -45 dBc after digital pre-distortion at 0.73, 1.18 and 1.85 GHz.

A 267 GHz Wide Tuning Range VCO With −3.5 dBm Peak Output Power in 40-nm CMOS

This article presents a highly efficient, wide tuning range push-push voltage-controlled oscillator (VCO) in the sub-terahertz frequency band. The proposed VCO adopted a novel capacitance-splitting feedback technique to achieve high oscillation frequency and output power. The frequency tuning is provided through a tunable source degeneration (TSD) network. The proposed TSD network enables a wide tuning range without substantially sacrificing output power. The proposed VCO is fabricated in a 40-nm complementary metal-oxide-semiconductor (CMOS) process and has a peak output power of −3.5 dBm, a center frequency of 267.2 GHz, and a continuous tuning range of 27 GHz. The VCO consumes 30 mA current from a 1.1 V dc supply, resulting in 1.35% dc-to-RF efficiency.

Efficient 6.5 dBm 55 GHz CMOS VCO with simultaneous phase noise and tuning range optimization

Abstract This paper presents the design and characterization of an efficient high-output-power 55 GHz fundamental oscillator. The performance parameters of the oscillator are analysed as a function of the contributors of the tank capacitance, and the design choices in the varactor for phase noise and for tuning range are exemplified. The circuit was implemented in 22 nm FD-SOI CMOS technology and occupies 0.046 mm2 area including the matching network. On-wafer measurement results have demonstrated 6.5 dBm peak output power, 22% peak DC-to-RF efficiency and −98.3 dBc/Hz phase noise at 1 MHz offset frequency, while the core draws 8.3 mW power. To the best knowledge of the authors, the efficiency is the best, while the output power is the second best among CMOS oscillators in the same frequency range, and the phase noise is the best result for V-band fundamental CMOS oscillators reported to date.

A Cascaded Multi-Drive Stacked-SOI Distributed Power Amplifier With 23.5 dBm Peak Output Power and Over 4.5-THz GBW

This article presents a cascaded distributed power amplifier (DPA) topology with greater than 4.5-THz gain-bandwidth (GBW) product. The DPA uses stacking with multi-drive inter-stack coupling to compensate for the stacked gain cells and input transmission-line (TL) losses. The techniques improve the gain and output power without compromising the bandwidth (BW). The cascaded DPA employs eight-shaped TLs to allow inter-stack coupling in a compact area and for field confinement. A 33-dB gain, 101.5 GHz BW DPA is realized in the 45-nm RFSOI GlobalFoundries process. The amplifier maintains P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> > 18.7 and 21 dBm, respectively, up to 60 GHz, with over 60 GHz P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> 3-dB BW, while demonstrating >14 dBm of average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> for a 30-Gb/s 64-QAM modulated signal, with an error vector magnitude (EVM) <; 5%. The DPA is also able to provide a 72-Gb/s 64-QAM signal with 13.6 dBm average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> from a 13 GHz carrier frequency. To the best of our knowledge, the cascaded multi-drive DPA achieves the highest reported GBW, continuous-wave (CW) P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> , and average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> for 64-QAM 30-Gb/s modulated signal, in a compact core area compared to published silicon-based DPAs with comparable power levels.

A High Efficiency Multi-Mode Outphasing RF Power Amplifier With 31.6 dBm Peak Output Power in 45nm CMOS

A high efficiency multi-mode class-E outphasing RF power amplifier (PA) with a passive combining circuit is presented. The multi-mode PA combines multiple class-E amplifier branches and can work in different configurations. The PA improves efficiency at lower power levels by switching ‘on’ and ‘off’ individual branches in a static or dynamic manner and using Efficiency Enhancement Circuit (EEC). The proposed power amplifier is designed in 45nm CMOS technology. The PA delivers 31.6 dBm peak output power at 2.4 GHz with 49.2% drain efficiency in high power single level mode. With 64-QAM long-term evolution (LTE) signal with 10 MHz and 20 MHz bandwidth, −57 dBc and −53 dBc adjacent channel power ratio (ACPR) are obtained in single level outphasing (SLO) mode after digital pre-distortion (DPD). 25% and 33% average drain efficiency are achieved with LTE signal with 6 dB peak-to-average power ratio (PAPR) in single level outphasing and asymmetric multilevel outphasing (AMO) mode, respectively. The PA satisfies the spectral mask requirement of 802.11g WLAN signal with high margin. Error vector magnitude (EVM) of 1.1% (−39.36 dB) is obtained from the PA in single level outphasing high power mode after DPD with 64-QAM LTE signal with 10 MHz bandwidth.

An RF Choke-Less Class E Power Amplifier

An RF-choke (RFC) is a crucial but difficult-to-realize component of all Class-E power amplifiers (PAs). A Class-DE PA does not require an RFC but requires two non-overlapping clocks for its operation. This brief presents an RFC-less Class-E PA which operates with a single 50% duty-cycled clock. Analytical expressions for the switch voltages and currents in the proposed PA are derived and validated. Design equations are provided. A prototype RFC-less Class-E PA is implemented in CMOS 180 nm technology. Measurements show that the PA can deliver +21.5 dBm peak output power at 1 GHz with a system efficiency of 41.1%. The measured second and third harmonic distortions at the peak power are −46 dBc and −48.47 dBc, respectively.

Efficient active multiplier‐based signal source for &gt;300 GHz system applications

This Letter presents a 300 GHz signal source, realised using an 800 nm transferred-substrate InP double heterojunction bipolar transistor process. The source is based on an active frequency tripler. It delivers −1.6 dBm peak output power at 306 GHz. The DC consumption is only 36 mW, which corresponds to 2% conversion efficiency. The measured tripler achieves more than 30 GHz bandwidth and exhibits very low unwanted harmonics. The chip area of the source is only 0.94 × 0.84 mm2.

A CMOS Wideband Current-Mode Digital Polar Power Amplifier With Built-In AM–PM Distortion Self-Compensation

This paper presents a fully integrated wideband current-mode digital polar power amplifier (DPA) in CMOS with built-in AM–PM distortion self-compensation. Feedforward capacitors are implemented in each differential cascode digital power cell. These feedforward capacitors operate together with a proposed DPA biasing scheme to minimize the DPA output device capacitance $C_{d}$ variations over a wide output power range and a wide carrier frequency bandwidth, resulting in DPA AM–PM distortion reduction. A three-coil transformer-based DPA output passive network is implemented within a single transformer footprint (330 $\mu \text{m} \,\, \times $ 330 $\mu \text{m}$ ) and provides parallel power combining and load impedance transformation with a low loss, an octave bandwidth, and a large impedance transformation ratio. Moreover, this proposed power amplifier (PA) output passive network shows a desensitized phase response to $C_{d}$ variations and further suppresses the DPA AM–PM distortion. Both proposed AM–PM distortion self-compensation techniques are effective for a large carrier frequency range and a wide modulation bandwidth, and are independent of the DPA AM control codes. This results in a superior inherent DPA phase linearity and reduces or even eliminates the need for phase pre-distortion, which dramatically simplifies the DPA pre-distortion computations. As a proof-of-concept, a 2–4.3 GHz wideband DPA is implemented in a standard 28-nm bulk CMOS process. Operating with a low supply voltage of 1.4 V for enhanced reliability, the DPA demonstrates ±0.5 dB PA output power bandwidth from 2 to 4.3 GHz with +24.9 dBm peak output power at 3.1 GHz. The measured peak PA drain efficiency is 42.7% at 2.5 GHz and is more than 27% from 2 to 4.3 GHz. The measured PA AM–PM distortion is within 6.8° at 2.8 GHz over the PA output power dynamic range of 25 dB, achieving the lowest AM–PM distortion among recently reported current-mode DPAs in the same frequency range. Without any phase pre-distortion, modulation measurements with a 20-MHz 802.11n standard compliant signal demonstrate 2.95% rms error vector magnitude, −33.5 dBc adjacent channel leakage ratio, 15.6% PA drain efficiency, and +14.6 dBm PA average output power at 2.8 GHz.

A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS

A CMOS class-E outphasing RF power amplifier is presented with a new passive combining circuit that provides high efficiency and high output power. An efficiency enhancement circuit and a power enhancement circuit are proposed as part of the combiner that improve efficiency at power back-off and increase output power without violating reliability limits, respectively. The proposed power amplifier is designed in a 45nm CMOS technology. The power amplifier (PA) delivers 29.5 dBm peak output power at 2.4 GHz with 46.76% drain efficiency at peak output power, 32.96% drain efficiency at 3 dB power back-off, and 21.16% drain efficiency at 6 dB power back-off. The proposed power amplifier shows excellent linearity with digital pre-distortion. Better than -50 dBc adjacent channel power ratio (ACPR) is obtained with 64-QAM long-term evolution (LTE) signal with 10 MHz and 20 MHz bandwidth. For two-carrier 20 MHz LTE signal, -44 dBc ACPR is achieved. 21% average drain efficiency is obtained with LTE signal with a 6 dB peak-to-average power ratio. The PA is also tested with 802.11g WLAN signal and it satisfies the spectral mask requirement with high margin. 1.4% (-37.1 dB) error vector magnitude (EVM) is obtained with LTE signal (64-QAM) with a 10 MHz bandwidth.

High-sensitivity sucrose erbium-doped fiber ring laser sensor

We investigate a high-sensitivity sucrose sensor based on a standard erbium-doped fiber ring laser incorporating a coreless fiber (CF). A single-mode-coreless-single mode (SCS) structure with a very low insertion loss has been constructed. The SCS fiber structure performed dual function as an intracavity fiber filter and/or a sensing element. The gain medium (erbium-doped fiber) is pumped by a 975-nm wavelength fiber coupled diode laser. Laser emission around 1537 nm with −2 dBm peak output power is obtained when a CF in SCS structure has a diameter of 125 μm. The 3-dB line-width of the laser is <0.14 nm, which is beneficial to high precision sensing. The sucrose concentration varied from 0% to 60%, and the relationship between the lasing wavelength and the sucrose concentration exhibited linear behavior (R2=0.996), with sensitivity of 0.16 nm/% was obtained. To improve the measurement sensitivity, the CF is etched by hydrofluoric acid. The splice joint of etched CF with SMF is a taper, which improves its sensitivity to sucrose changes. An average sensitivity of 0.57 nm/% and a high signal-to-noise ratio of 50 dB make the proposed sensor suitable for potential applications.

A Wideband 20 to 28 GHz Signal Generator MMIC With 30.8 dBm Output Power Based on a Power Amplifier Cell With 31% PAE in SiGe

High-frequency systems such as mm-wave radar transmitters and LO/RF driver chains in vector network analyzers (VNAs) often require the generation of signals with high output power. While these systems benefit considerably from the reduction in size and cost provided by SiGe integration, their output power must be further increased in order to meet the performance of other technologies (e.g., GaAs). To this end, a SiGe signal generator MMIC was developed that achieves 28.7 dBm peak output power with 21.9% PAE and over 27.4 dBm of output power over the whole frequency range from 19.7 GHz to 28.2 GHz. The output power is scalable with DC current up to a maximum of 30.8 dBm. The signal generator is based on a VCO, power amplifier cells (PA cells) and lumped-element Wilkinson power combiners/dividers. The VCO’s phase noise is less than −96 dBc/Hz at 1 MHz offset over the entire frequency range. The developed single PA cell achieves a maximum saturated output power $P_{\mathrm {sat}}$ of 24.7 dBm with peak PAE of 31%. This article describes the design and performance of all components. The signal generator MMIC has been integrated in an evaluation board together with a PLL, power supply, and serial interface.

Highly efficient W‐band 2.5 GHz bandwidth pulse generator with −1 dBm output power in 65 nm CMOS

A W-band 2.5 GHz bandwidth pulse generator comprising a voltage-controlled oscillator (VCO) and a novel pulse former in a 65 nm CMOS technology is presented. The proposed sub-harmonic pumped pulse former, which plays roles as both a frequency doubler and a pulse former, is designed to obtain high efficiency using a transformer-based current reuse circuit. The VCO is implemented with a parallel combining transformer, which makes it insensitive to load variations due to pulse formation. Measurements show that the pulse generator achieves −1 dBm peak output power at 79 GHz. It can generate 800 ps pulse signals with an RF carrier of 76.1–79.6 GHz, achieving the energy cost rate of 50 pJ/pulse with a 1.25 GHz pulse repetition period.

Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS

This paper presents a digital polar Doherty power amplifier (PA) fully integrated in a 65 nm bulk CMOS process. It achieves +27.3 dBm peak output power and 32.5% peak PA drain efficiency at 3.82 GHz and 3.60 GHz, respectively. The proposed digital Doherty PA architecture optimizes the cooperation of the main and auxiliary amplifiers and achieves superior back-off efficiency enhancement (a maximum 47.9% improvement versus the corresponding Class-B operation). This digital intensive architecture also allows in-field PA reconfigurability which both provides robust PA operation against antenna mismatches and allows flexible trade-off optimization on PA efficiency and linearity. Transformer-based passives are employed as the Doherty input and output networks. The input 90 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> signal splitter is realized by a 6-port folded differential transformer structure. The active Doherty load modulation and power combining at the PA output are achieved by two transformers in a parallel configuration. These transformer-based passives ensure an ultra-compact PA design (2.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and broad bandwidth (24.9% for -1 dB P out bandwidth). Measurement with 1 MSym/s QPSK signal shows 3.5% rms EVM with +23.5 dBm average output power and 26.8% PA drain efficiency. Measurement with 16-QAM signal exhibits the PA's flexibility on optimizing efficiency and linearity.

A Compact Single Stage V-Band CMOS Injection-Locked Power Amplifier With 17.3% Efficiency

This letter presents a fully integrated CMOS V-band injection-locked power amplifier (ILPA) for phase and frequency modulated millimeter-Wave (mm-Wave) transmitter. At mm-Wave frequency, multi-stage PAs are usually employed to achieve enough power gain due to low power gain of CMOS transistor even though it has low power efficiency. This work investigates mm-Wave ILPA for constant envelope modulation transmitter with high gain and high efficiency. The proposed ILPA has been implemented in 65 nm CMOS technology, a 17.3% Power Added Efficiency (PAE) and 9.6 dBm peak output power have been achieved with a single stage design in a compact size at 1.2 V supply voltage.

A reconfigurable multi-mode multi-band transmitter with integrated frequency synthesizer for short-range wireless communication

A reconfigurable multi-mode direct-conversion transmitter (TX) with integrated frequency synthesizer (FS) is presented. The TX as well as the FS is designed with a flexible architecture and frequency plan, which helps to support all the 433/868/915 MHz ISM band signals, with the reconfigurable bandwidth from 250 kHz to 2 MHz. In order to save power and chip area, only one 1.8 GHz VCO is adopted to cover the whole frequency range. All the operation modes can be regulated in real time by configuring the integrated register-bank through an SPI interface. Implemented in 180 nm CMOS, the FS achieves a frequency coverage of 320–460 MHz and 620–920 MHz. The lowest phase noise can be −107 dBc/Hz at a 100 kHz offset and −126 dBc/Hz at a 1 MHz offset. The transmitter features a + 10.2 dBm peak output power with a +9.5 dBm 1-dB-compression point and 250 kHz/500 kHz/1 MHz/2 MHz reconfigurable signal bandwidth.

Analysis and Optimization of Transformer-Based Power Combining for Back-Off Efficiency Enhancement

This paper analyzes the back-off efficiency enhancement characteristics of transformer combined power amplifiers taking into account the amplifier and transformer parasitics. The dynamic power combining properties of different transformer architectures are investigated. The co-optimization of the transformer and the amplifiers is presented for the transformer-based Doherty power amplifier which is a linear class of operation with back-off efficiency enhancement. Then this analysis is extended for the uneven Doherty power amplifier which employs asymmetrical transformers. The proposed design methodology is used to design a 2.4 GHz uneven Doherty power amplifier in standard 90 nm CMOS technology. The fabricated two stage Doherty amplifier achieves 26.2 dBm peak output power at 2 V supply. The measured peak drain efficiency of the PA is 37% while the efficiency at 6 dB back-off is still as high as 30.1%.

Design of C-Band High Speed Pulsed Power Amplifier for Pulsed RADAR Applications

This paper describes the design and development of a narrow band two stage high speed Solid State Pulsed Power Amplifier (SS-PPA) working at 7.23 GHz frequency. The amplifier is designed by using commercial packaged PHEMTs. A pulse aggregate card has been developed to provide modulated pulsed bias. At room temperature, the PPA provides 17.58 dB gain yielding 26.58 dBm peak output power for 9 dBm input driving power. The measured rise and fall time of the final prototype is obtained as 25.0 ns and 19.2 ns respectively at 90 ns Pulse Width (PW) with 30 kHz Pulse Repetition Frequency (PRF). We report a description of the design of the amplifier along with an account of its performance made through a comparison of simulated and measured results with desired target specifications.

A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement

A transformer-combined fully integrated outphasing class-D PA in 45 nm LP CMOS achieves 31.5 dBm peak output power at 2.4 GHz with 27% peak PAE, and supports over 86 dB of output power range. The PA employs dynamic power control (DPC) whereby sections of the PA are turned on or off dynamically according to the instantaneous signal amplitude to reduce power dissipation, especially at back-off. Dynamic on-off switching introduces transients on the power supply that can limit performance. The paper proposes and demonstrates techniques to reduce the impact of such transients. A multi-section slab inductor based transformer combiner is used to allow individual switching of unit PAs. The PA delivers 24.8 dBm average power while meeting 64-QAM WLAN requirements. PAE is 16% when using DPC, which represents a 33% efficiency enhancement compared to the DPC-disabled mode. At lower average power of 20.5 dBm, DPC enables a 140% enhancement in average efficiency, hence increasing battery life.

A broadband GaAs MMIC frequency doubler on left-handed nonlinear transmission lines

A broadband frequency doubler using left-handed nonlinear transmission lines (LH NLTLs) based on MMIC technology is reported for the first time. The second harmonic generation on LH NLTLs was analyzed theoretically. A four-section LH NLTL which has a layout of 5.4 × 0.8 mm2 was fabricated on GaAs semi-insulating substrate. With 20-dBm input power, the doubler obtained 6.33 dBm peak output power at 26.8 GHz with 24–43 GHz −6 dBm bandwidth. The experimental results were quite consistent with the simulated results. The compactness and the broad band characteristics of the circuit make it well suit for GaAs RF/MMIC application.