dBc Reference Spur Research Articles

A 28.8-to-43.2 GHz 79.8 fsrms Jitter and −78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration

A 28.8-to-43.2 GHz 79.8 fs_rms Jitter and −78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration

A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology

A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology

A Flexible 0.73–15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS

This brief presents a compact and flexible 0.73–15.5GHz clock generator with only a single LC-VCO. A 50% duty cycle divide-by-1.5 divider (Div-1.5) is employed to reduce the required VCO tuning range in the wide-range clock generator to 50%, which becomes viable for a single LC-VCO to cover. The divider is realized by duty cycle interpolation (DI) between two digital divide-by-1.5 (DDiv-1.5) clocks with 33.3% duty cycle and 66.7% duty cycle, respectively. The clock generator was fabricated in 12nm CMOS process with an active area of 0.17 mm2. At a 13.28125GHz output, it achieves a 101fs integrated jitter and a −74.79dBc reference spur, while consuming 19.5mW. The measured worst deterministic jitter induced by the 50% duty cycle Div-1.5 is 550fs.

28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-N PLL for 2.4-GHz Internet-of-Things Applications

This article presents a 2.4-GHz low-power compact integer-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> ring oscillator-based phase-locked loop (PLL) for Internet of Things (IoT) applications. The proposed integer-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL is based on a dual loop Offset-PLL topology to achieve a fine frequency resolution similar to conventional fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL. Not using a delta-sigma modulator (DSM) allows an expanded PLL bandwidth without deteriorating the overall noise performance. Implemented in 28 nm CMOS fully depleted silicon on insulator (FD-SOI) technology, the proposed architecture requires a 22-MHz internal reference frequency while achieving a 2-MHz frequency resolution and a 3-MHz PLL bandwidth. Measured prototypes perform &#x2212;43.9 dBc reference spur, as an average value over all the bluetooth low energy (BLE) band and numerous tested dies, a jitter Figure-of-Merit of &#x2212;229.6 dB for a power consumption of 0.87 mW and a core area of 0.0256 mm².

High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks

One of the most promising solutions for the future fifth generation communication systems is to utilize millimeter wave (mm-W) radio frequencies. There is, however, little works about Phase Locked Loop (PLL) frequency synthesizer designed for mm-W band frequency for 5G applications. This article discusses integer PLL architecture for frequency synthesis; it targets the highest range of 5G mmW [81–86] GHz using ultra-wide channel spacing of 1 GHz. This work investigates the design of a third passive loop filter for frequency synthesizer using a Phase Frequency Detector and a current switch Charge Pump such as analog devices ADF4155. The critical performance for the Charge Pump depends on the leakage current produced by the technology of its transistors. This undesirable current can have a high impact on the loop stability. However, by optimizing PLL filter parameters, the synthesizer was able to tolerate up to 117 nA. With such a high leakage current, a high performance of the system was achieved. As a result, less than −71 dBc reference spur level at 50 MHz offset frequency was ensured and 3.23 µs settling time for a hopping frequency of 5 GHz was achieved.

A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis

A multiplying delay-locked loop (MDLL)-based clock multiplier with a two-step phase aligning architecture and a dual-pulse charge-pump (CP) is proposed to reduce the reference spur level. The architecture has a phase-locked loop mode to align the coarse phase and an MDLL mode to obtain a delay-lock. With non-overlap dual phase detector pulses in the MDLL mode, the CP is directly calibrated in the runtime to minimize its phase offset. A discrete-time noise transfer function (NTF) is also derived to estimate the phase noise of multiplying-delay line from that of delay line. The NTF includes aliasing effect and shows better accuracy than the prior voltage controlled oscillator realignment-based approaches. This clock multiplier occupies an active area of 0.047-mm2 in 40-nm CMOS process. The clock multiplication ratio ( $N$ ) is an integer value from 8 to 27. With a low-cost 19.2-MHz TCXO reference, 153.6–518.4 MHz clocks were successfully generated, and a phase noise of −124 dBc/Hz at 100-kHz offset from a 518.4-MHz clock, rms jitter of 1.28 ps, and −65.5 dBc reference spur were measured. The power dissipation at 518.4 MHz was 2.6 mW from the 1.8 and 1.1 V supplies.

A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

This paper presents a 5.7–6.0 GHz Phase-Locked Loop (PLL) design using a 130 nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (KVCO). With a reference frequency of 32.768 MHz, chip measurement results show that the frequency tuning range is 5.7–6.0 GHz, the reference spur is −68 dBc, the phase noise levels are −109 dBc/Hz and −135 dBc/Hz at 1 MHz and 10 MHz offset respectively for 5.835 GHz. Compared with existing designs in the literature, this work’s reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5 V supply voltage, the power dissipation with an output buffer of the PLL is 12 mW.

A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques

This paper presents a digital bang–bang phase-locked loop (DBPLL) that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. Due to noise filtering properties, a DBPLL has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the automatic loop gain control technique, the DBPLL can automatically attain this loop gain in background to minimize the jitter. This paper also exploits time-series analysis to analyze the DBPLL. In particular, the closed-form gain of a bang–bang phase detector (BBPD) is first derived, taking into account reference clock noise and oscillator noise simultaneously. The chip was fabricated in a 40 nm CMOS process. This DBPLL achieves $ fs integrated rms jitter and $ dBc reference spurs. It consumes 3.8 mW from a 1.1 V supply while operating at 3.96 GHz. This translates to an figure-of-merit (FOM) of $- 245$ dB.

A reduced reference spur multiplying delay‐locked loop

SummaryThis letter presents a reduced reference spur multiplying delay‐locked loop (MDLL). The static phase offset (SPO) between the reference edge and its counterpart of MDLL output is the dominant mechanism causing reference spur in the spectrum of MDLL output. SPO is mainly caused by the non‐idealities on charge pump (e.g., sink and source current mismatch) and control line (e.g., gate leakage of loop filter and voltage‐controlled delay line control circuit). With a high‐gain stage inserting between phase detector/phase frequency detector and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. To validate the effectiveness of the proposed technique, an MDLL is implemented in TSMC CMOS 0.18 µm process. The simulation result shows that −60.1 dBc reference spur was achieved at center frequency of 1.8 GHz. Copyright © 2015 John Wiley &amp; Sons, Ltd.

A 2 GHz 2 Mb/s Semi-Digital &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$2^{+}$&lt;/tex&gt;&lt;/formula&gt;-Point Modulator With Separate FIR-Embedded 1-Bit DCO Modulation in 0.18 &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\mu$&lt;/tex&gt; &lt;/formula&gt;m CMOS

A 2 GHz two-point modulator which has a separate high-pass control for DCO modulation is implemented in 0.18 μm CMOS. The proposed modulator with the two-path DCO modulation enables a flexible gain partition for the high-pass and low-pass modulation paths within the DCO and relaxes the DCO nonlinearity with 1-b ΔΣ modulation and embedded finite-impulse response (FIR) filtering. A semi-digital ΔΣ PLL with another FIR filtering in the low-pass modulation enhances PLL linearity with a hybrid loop control. The proposed semi-digital modulator achieves 2.03% RMS EVM with 2 Mb/s GFSK modulation, -132 dBc/Hz phase noise at 3 MHz offset, and -80 dBc reference spur.

Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump

A clock multiplier combines the low reference spur of a PLL with the low phase noise of a recirculating DLL. It uses a ring oscillator that has two pulses running simultaneously that are phase independent. One pulse is used by a PLL to precisely set ring delay while the other pulse is periodically realigned with the reference phase by a process of pulse removal and reinsertion, similar to a DLL. The DLL reference spur due to static phase offset is eliminated, since the realigned pulse is not used to control the delay. A self-correcting charge pump is introduced that corrects for mismatches in the actual up-and down currents. The 0.048 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 90 nm CMOS circuit has -122 dBc/Hz phase noise @ 200 kHz offset of an 800 MHz carrier, - 48 dBc reference spur and consumes 15 mW from a 1 V supply.

Notice of Violation of IEEE Publication Principles: A low reference spurs 1-5 GHz 0.13 μm CMOS frequency synthesizer using a fully-sampled feed-forward loop filter architecture

Notice of Violation of IEEE Publication Principles<br><br>"A Low Reference Spurs 15 GHz 0.13 μm CMOS Frequency Synthesizer Using a Fully-Sampled Feed-Forward Loop Filter Architecture"<br>by Maxim, A.<br>in the IEEE Journal of Solid-State Circuits,<br>Volume 42, Issue 11, Nov. 2007 Page(s):2503 - 2514<br><br>After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.<br><br>Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:<br><br>C. Turinici, D. Smith, S. Dupue<br><br>Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.<br><br>Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.<br><br>Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references. <br/> A wide tuning range, low phase noise and spurs, multi-gigahertz frequency synthesizer was realized in 0.13 μm CMOS using a fully-sampled feed-forward loop filter. Both the integral and proportional loop filter paths use sample and hold switched-capacitor networks that completely isolate the oscillator from the charge-pump switching transients. The sampled nature of the filter, together with a digital domain implementation of the ripple-filtering pole spread the impulsive energy coming from the charge-pump current injection over several reference clock cycles, resulting in a dramatic reduction of the oscillator control signal ripple and thus a very low reference spur level. A multi-regulator PLL architecture reduces the supply injected noise and spurious tones, allowing the integration of the synthesizer on the same die with a large digital core, as required by modern single-chip receiver SoCs. PLL specifications include: < 1deg rms double-sided integrated phase noise from 1 kHz to 10 MHz, -85 dBc reference spurs, < -80 dBc supply injected spurs, 300 times 750 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area and < 100 mW power dissipation from a single 2.5 V supply.

A DLL-Based Programmable Clock Multiplier in 0.18-$\mu$m CMOS With ${-}$70 dBc Reference Spur

This paper describes a 150-400 MHz programmable clock multiplier which uses a recirculating DLL. The clock multiplier uses a sampling phase detector and employs chopping, autozeroing and various other circuit techniques to reduce static phase offset and crosstalk between the reference and the output clock. The DLL is implemented in 0.18-mum CMOS, consumes 16 mW of power, and achieves 1-5 ps RMS jitter and -70 dBc reference spur level.

Current-Mode Phase-Locked Loops&amp;mdash; A New Architecture

This brief introduces current-mode phase-locked loops (PLLs). The proposed current-mode PLLs differ from conventional voltage-mode PLLs by replacing their RC loop filter with a RL loop filter, eliminating the need for large on-chip capacitors. The large inductance of the current-mode loop filter is obtained from CMOS active inductors, taking the advantage of their large and tunable inductance and small silicon area. Both types I and II current-mode PLLs are introduced. Implemented in TSMC 0.18-mum CMOS technology, the simulation results of a 3-GHz current-mode PLL demonstrate that the PLL has the lock time 50 ns, silicon area 2800 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , dc power consumption 12.2 mW, and phase noise of -84.5 dBc at 1-MHz frequency offset and the maximum -74 dBc reference spurs