28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-N PLL for 2.4-GHz Internet-of-Things Applications

Abstract

This article presents a 2.4-GHz low-power compact integer-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> ring oscillator-based phase-locked loop (PLL) for Internet of Things (IoT) applications. The proposed integer-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL is based on a dual loop Offset-PLL topology to achieve a fine frequency resolution similar to conventional fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL. Not using a delta-sigma modulator (DSM) allows an expanded PLL bandwidth without deteriorating the overall noise performance. Implemented in 28 nm CMOS fully depleted silicon on insulator (FD-SOI) technology, the proposed architecture requires a 22-MHz internal reference frequency while achieving a 2-MHz frequency resolution and a 3-MHz PLL bandwidth. Measured prototypes perform &#x2212;43.9 dBc reference spur, as an average value over all the bluetooth low energy (BLE) band and numerous tested dies, a jitter Figure-of-Merit of &#x2212;229.6 dB for a power consumption of 0.87 mW and a core area of 0.0256 mm².