Datapath Architecture Research Articles

HLS‐based swarm intelligence driven optimized hardware IP core for linear regression‐based machine learning

AbstractLinear Regression (LR), as one of the essential Machine Learning (ML) models, incurs massive data crunching during the training phase based on many data points. Considering the computationally intensive nature in the LR models, an optimized dedicated hardware IP core design can be very effective. This paper proposes the following novelties: (a) an optimized hardware IP core design of linear regression‐based machine learning model using high‐level synthesis (HLS). More specifically, independent application specific datapath architectures of hardware IP for computing optimal bias and intercepts and cost function in LR‐ML are presented here; (b) an optimized hardware IP core design of LR based ML model by deducing dependency graph from its corresponding mathematical foundation; (c) register transfer level (RTL) design, using HLS, of the optimized LR based ML hardware IP core for computing cost function; (d) linear regression IP core design using multi‐layered tree‐height transformation (THT) and swarm intelligence based architectural exploration for optimized HLS design.

MaskSIMD-lib: on the performance gap of a generic C optimized assembly and wide vector extensions for masked software with an Ascon-p test case

Efficient implementations of software masked designs constitute both an important goal and a significant challenge to Side Channel Analysis attack (SCA) security. In this paper we discuss the shortfall between generic C implementations and optimized (inline-) assembly versions while providing a large spectrum of efficient and generic masked implementations for any order, and demonstrate cryptographic algorithms and masking gadgets with reference to the state of the art. Our main goal is to show the prime performance gaps we can expect between different implementations and suggest how to harness the underlying hardware efficiently, a daunting task for various masking-orders or masking algorithm (multiplications, refreshing etc.). This paper focuses on implementations targeting wide vector bitsliced designs, such as the ISAP algorithm. We explore concrete instances of implementations utilizing processors enabled by wide-vector capability extensions of the AMD64 Instruction Set Architecture (ISA); namely, the SSE2/3/4.1, AVX-2 and AVX-512 Streaming Single Instruction Multiple Data extensions. These extensions mainly enable efficient memory level parallelism and provide a gradual reduction in computation-time as a function of the level of extension and the hardware support for instruction-level parallelism. For the first time we provide a complete open-source repository of such gadgets tailored for these extensions, various gadgets types and for all orders. We evaluate the disparities between generic high-level language masking implementations for optimized (inline-) assembly and conventional single execution path data-path architectures such as the ARM architecture. We underscore the crucial trade-off between state storage in the data-memory as compared to keeping it in the register-file (RF). This relates specifically to masked designs, and is particularly difficult to resolve because it requires inline-assembly manipulations and is not natively supported by compilers. Moreover, as the masking order (d) increases and the state gets larger, there must be an increase in data memory read/write accesses for state handling since the RF is simply not large enough. This requires careful optimization which depends to a considerable extent on the underlying algorithm to implement. We discuss how full utilization of SSE extensions is not always possible; i.e. when d is not a power of two, and pin-point the optimal d values and very sub-optimal values of d which aggressively under-utilize the hardware. More generally, this paper presents several different fully generic masked implementations for any order or multiple highly optimized (inline-) assembly instances which are quite generic (for a wide spectrum of ISAs and extensions), and provide very specific implementations targeting specific extensions. The goal is to promote open-source availability, research, improvement and implementations relating to SCA security and masked designs. The building blocks and methodologies provided here are portable and can be easily adapted to other algorithms.

PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis

Image processing filter intellectual property (IP) cores perform different critical operations on images such as blurring, sharpening, edge detection, etc., which are essential functions in several multimedia systems. The design process of the image filter cores as a dedicated IP needs to consider multiple objectives such as area, delay, and security against various hardware threats such as IP piracy (counterfeiting and cloning) and fraudulent claim of IP ownership during design space exploration (DSE) in high level synthesis (HLS). This paper presents the following novelties: (a) particle swarm optimization (PSO) driven exploration of secured image processing filter IP core datapath architecture during HLS capable of providing detective control against IP piracy threat (b) the proposed approach incorporates embedding of covert security constraints based on the proposed multi-phase encryption algorithm during performing area-delay tradeoff via PSO based DSE. The proposed approach achieves stronger security in terms of digital proof of > 2X and higher tamper tolerance as well as attains a lower design cost of 56.92% in terms of area-delay than recent approaches. The proposed approach also achieves optimal solution as evident from the optimality analysis performed on metrics such as generational distance, spacing, spreading, and weighted sum.

ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters

This paper proposes ReAdapt–a reconfigurable datapath architecture for scaling the energy-quality trade-off of adaptive filtering at runtime. The ReAdapt can dynamically select four adaptive filtering algorithms for gradating complexity levels during runtime by reconfiguring the processing flow in its datapath and by blocking the switching activity (e.g., reducing the CMOS dynamic power) of unused modules with data-gating. The ReAdapt proposal can scale the energy-quality trade-off by choosing the following four different levels of filter algorithms complexity: 1) least mean square (LMS); 2) partial update normalized LMS (PU-NLMS); 3) set-membership normalized LMS (SM-NLMS); 4) normalized LMS (NLMS). The ReAdapt architecture reuses common modules of each adaptive filter, resulting in a compact VLSI hardware implementation. The ReAdapt architecture operation is implemented in a case-study for interference mitigation for electroencephalogram (EEG) signal processing. The hardware synthesis results show an increase of 6.80 times in throughput and at least a reduction of 2.84 times in energy per operation compared with the state-of-the-art adaptive filters. This paper also investigates the benefits of dynamically reconfiguring the four ReAdapt operating modes at runtime for different levels of signal-to-noise ratio (SNR) for the processed signals. We also demonstrate that dynamically reconfiguring the ReAdapt operating modes during runtime results in an optimal energy-quality trade-off which is advantageous over the conventional single static mode.

CUTIE: Beyond PetaOp/s/W Ternary DNN Inference Acceleration With Better-Than-Binary Energy Efficiency

We present a 3.1 POp/s/W fully digital hardware accelerator for ternary neural networks (TNNs). CUTIE, the completely unrolled ternary inference engine, focuses on minimizing noncomputational energy and switching activity so that dynamic power spent on storing (locally or globally) intermediate results is minimized. This is achieved by: 1) a data-path architecture completely unrolled in the feature map and filter dimensions to reduce switching activity by favoring silencing over iterative computation and maximizing data reuse; 2) targeting TNNs which, in contrast to binary NNs, allow for sparse weights that reduce switching activity; and 3) introducing an optimized training method for higher sparsity of the filter weights, resulting in a further reduction of the switching activity. Compared with state-of-the-art accelerators, CUTIE achieves greater or equal accuracy while decreasing the overall core inference energy cost by a factor of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.8\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$21\times $ </tex-math></inline-formula> .

A new ASIC implementation of an advanced encryption standard (AES) crypto-hardware accelerator

Single-chip hardware implementation of Advanced Encryption Standard (AES) offers a low-power and low-area design that is suitable for portable devices. It is widely applicable for numerous encryption needs such as in Bluetooth controller, wireless communication and secure Internet transactions. This paper proposes a new full-custom compact 8-bit data-path architecture core for a single-chip VLSI AES crypto-hardware accelerator. In order to optimize chip-area, power and performance, novel circuit-level techniques, logic minimization, resource sharing and low supply-voltage has been employed. The proposed design is implemented in 130 nm CMOS process and supports both encryption and decryption in Electronic-Codebook-Mode (EBC) using 128-bit keys. Novel S-box/InvS-box, MixColumn/InvMixColumn and ShiftRow/InvShiftRow using low-power Exclusive-OR (XOR) gate is employed to minimize the power consumption. This design utilized 3120 gate-equivalents (GE), including an on-the-fly key scheduling unit with an active chip-area of 640μm × 325 μm (0.208 sq. mm) excluding the bonding pads. It has a power consumption of 4.23 μW/MHz and a throughput of 0.05 Gbit/s (at 100 MHz clock). The proposed AES design thus achieved low-power dissipation, higher throughput with a compact chip-size (silicon-area) compared to other recent implementations.

Real-time implementation of fast discriminative scale space tracking algorithm

Real-time object tracking is an important step of many modern image processing applications. The efficient hardware design of real-time object tracker must achieve the desired accuracy while satisfying the frame rate requirements for a variety of image sizes. The existing methods of visual tracking employ sophisticated algorithms and challenge the capabilities of most embedded architectures. Discriminative scale space tracking is one algorithm that is capable of demonstrating good performance with affordable complexity. It has a high degree of parallelism which can be exploited for efficient implementation of reconfigurable hardware architectures. This paper proposes a real-time implementation of the discriminative scale-space tracker on FPGA for the major blocks. A careful design exploration of core mathematical operations of the tracking algorithm is performed to improve their hardware utilization and timing performance. Among the core functional units optimized in this work, the discrete Fourier transform achieves a computational time improvement of 92% relative to existing works, QR factorization achieves a 2.3times reduction in resource utilization, and singular value decomposition yields a 3.8times improvement in processing time. The proposed data path architecture is designed using Vivado HLS tool set and implemented for Zync Zed Board (xc7z020clg484-1). For an input image size of 320 times 240, the proposed architecture achieves a mean 25.38 fps.

Design and analysis of high performance and low power FFT for DSP datapath using Vedic Multipliers

ABSTRACT Fast Fourier Transform is one of the most efficient methods of performing computation in Digital signal processing blocks. These computations are basically performed by the inherent floating-point multiplier units residing inside the butterfly units of any FFT. To optimise an FFT for higher efficiency and performance, it is inevitable to use highly efficient adder and multiplier units within the datapath architecture of a FFT processor. This work proposes high-performance FFT units designed using optimised Vedic multiplier units for DSP processor cores. Choice of Vedic multiplier decreases power and delay overheads of design which leads to production of an efficient FFT. A comparative analysis is presented for 24-bit Vedic multiplier using nine adder variants. A separate analysis of inherent adders is also done. Using the two best proposed Vedic multipliers, FFT units of 8, 16 and 64-point are designed respectively. The designed FFT units are compared for dynamic power, area and delay with existing designs and an analysis is presented. Power efficiency of nearly 25% and delay efficiency of around 50% is achieved with respect to the existing designs. The design is simulated on Virtex-7 FPGA using Verilog HDL.

Implementation of Two-Dimensional (2D) Discrete Cosine Transform (DCT) using Reversible Gates

This research work presents the application-specific integrated circuit (ASIC) implementation of one dimensional (1 × 8) and two dimensional (8 × 8) discrete cosine transform using the reversible logic gates. During the DCT implementation, the integer DCT method of realization is adopted, thereby eliminating the occurrence of floating-point operations in the data path architecture. Thus, the integer mode of DCT realization using reversible logic gates in the proposed DCT architecture improves the delay, power and area of the 1D and 2D DCT data path structure when compared with the normal real DCT implementation. The proposed methodology of DCT implementation includes the construction of full adder and full subtractor using reversible gates and then extended for the realization of the DCT butterfly structure. Especially in this research method, Peres reversible gate is used for the implementation of full-adder and Thapliyal Ranganathan (TR) gate for the implementation of full subtractor, respectively. Thus, the 1D and 2D DCT implementation using reversible logic gates in 180nm technology nodes consume an overall area of 55504.311 sq.µm and 1122324.044 sq.µm respectively.

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

Circuit and design techniques are presented for enhancing the performance and reliability of a 3-D-stacked high bandwidth memory-2 extension (HBM2E). A data-bus window extension technique is implemented to cope with reduced clock cycle time ranging from data-path architecture, through-silicon via (TSV) placement, and TSV-PHY alignment. A power TSV placement in the middle of array and at the chip edge along with a dedicated top metal for power mesh improves power IR drop by 62%. An on-die ECC (OD-ECC) scheme featuring a self-scrubbing function is designed to be orthogonal to system ECC. An uncorrectable bit error rate (UBER) is improved by 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> times with the proposed OD-ECC and scrubbing scheme. A memory built-in self-test (MBIST) block supports low-frequency cell and core test in a parallel manner and all channel at-speed operation with adjustable ac parameters. The proposed parallel-bit MBIST reduces test time by 66%. A 16-GB HBM2E fabricated in the second generation of 10-nm class DRAM process achieves a bandwidth up to 640 GB/s (5 Gb/s/pin) and provides a stable bit-cell operation at a high temperature (e.g., 105 ° C).

SliceNetVSwitch: Definition, Design and Implementation of 5G Multi-Tenant Network Slicing in Software Data Paths

Network slicing is a primary Fifth-Generation (5G) mobile networking technology to create virtualised and softwarised logical networks for various vertical businesses with diverging Quality of Service (QoS) requirements. Meanwhile, there is a clear gap in providing network slicing capabilities in 5G multi-tenant networks to enable guaranteed QoS in terms of well-defined network metrics for the multiple tenants sharing the same physical infrastructure. This article designs and implements novel software data path architecture that enables such network slicing with assured QoS in 5G multi-tenant networks. Highly flexible and customisable definition of network slicing is also allowed to be aligned with different existing definitions on demand and at run time. The proposed architecture has been prototyped based on the popular Open Virtual Switch (OVS), and empirically validated to demonstrate the deployment and management of network slices with the above capabilities. Intensive scalability results are provided where more than 8,192 network slices are achieved simultaneously with warranted QoS through performance isolation in terms of bandwidth and delay in a real softwarised 5G multi-tenant infrastructure at speeds of up to 10 Gbps.

Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications

Advanced Internet-of-Things applications require control-oriented codes to be executed with low latency for fast responsivity while their advanced signal processing and decision making tasks require computational capabilities. For this context, we propose three multi-issue core designs featuring an exposed datapath architecture with high performance, while retaining energy-efficiency. These features are achieved with exploitation of instruction-level parallelism, fast branching and the use of an instruction register file. With benchmarks in control-flow and signal processing application domains we measured in the best case 64% reduced energy consumption compared to a state-of-the-art RISC core, while consuming less silicon area. A high-performance design point reaches nearly 2.6 GHz operating frequency in the best case, over 2× improvement, while simultaneously achieving a 14% improvement in system energy-delay product.

A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices With Speech Intelligibility Enhancement

This paper presents a low-power, programmable acoustic signal processor for hearing assistive devices with speech intelligibility enhancement. The reprogrammable design provides considerable flexibility for the devices to deal with personal conditions of hearing loss. A spectral-change enhancement (SCE) algorithm is implemented to improve speech intelligibility. The power consumption is minimized by adding dedicated hardware accelerators. The short-time objective intelligibility (STOI) measure is utilized for optimizing the datapath architecture. Optimization on the critical MAC operations results in 34% power and area reductions when compared to the direct-mapped design. A 50% reduction in SRAM storage is also achieved owing to the reduced memory storage for the associated MAC operations. With the aid of the optimized MAC unit and data buffer, the overall execution time is reduced by 99.2%. Designed in a 40-nm CMOS technology, the processor integrates 431k gates in area of 0.3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The design dissipates 1.5 mW at a clock frequency of 10.5 MHz from a 0.7V supply, with a processing latency of 1.05 ms.

Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA

Since the dawn of the Internet of Things (IoT), data and system security has been the major concern for developers. Because most IoT devices operate on 8-bit controllers with limited storage and computation power, encryption and decryption need to be implemented at the transmitting and receiving ends, respectively, using lightweight ciphers. We present novel architectures for hardware implementation for the ANU cipher and present results associated with each architecture. The ANU cipher is implemented at 4-, 8-, 16-, and 32-bit datapath sizes on four different field-programmable gate array (FPGA) platforms under the same implementation condition, and the results are compared on every performance metric. Unlike previous ANU architectures, the new architectures have parallel substitution boxes (S-boxes) for high throughput and hardware optimization. With these different datapath designs, ANU cipher proves to be the obvious choice for implementing security in extremely resource-constrained systems.

Efficient hardware implementations of QTL cipher for RFID applications

Extensive deployment of ubiquitous computing devices brings wide range of privacy and security issues in the low-resource domain. Various lightweight algorithms are proposed to solve security problem for these resource-constrained environments. In this work, optimised hardware implementations of lightweight block cipher QTL are proposed in order to provide security with optimum resource utilisation. In proposed reduced datapath architecture, resource utilisation is reduced and it gives good trade-off between area and performance. In proposed pipelined architecture, encryption round is divided into two sub-stages. This design methodology significantly improves the operating frequency. As a result, this design is apt for high-speed applications. Moreover, the proposed unified architecture combines three key scheduling designs into single design for QTL encryption and provides flexible security. All three architectures are extensively evaluated and compared on the basis of performance, area utilisation, energy requirement and power consumption for their implementations in different FPGA platforms.

Impact of hardware steganography on DSP core datapath

The protection of Intellectual Property (IP) core for a Digital Signal Processing (DSP) kernel has become an important research area in the last few years for Consumer Electronics systems. The swelling threats of IP piracy, forgery, and counterfeiting and ownership abuse on DSP IP core are the principal reason behind that. This work investigates the impact of hardware steganography on protection of DSP IP core datapath against these threats. As a case study, the complete analysis of its impact on 8-point Discrete Cosine Transformation datapath architecture is presented.

Enhanced SPIHT Algorithm with Pipelined Datapath Architecture Design

DOI : 10.26650/electrica.2018.15101 Set partitioning in hierarchical trees (SPIHT) is an efficient algorithm which is used for the image compression widely. SPIHT operates sequentially so, its parallel implementation is difficult. In this study, the SPIHT algorithm is improved for providing that it is suitable for the parallel processing applications, and the corresponding pipelined datapath is designed for the proposed enhanced SPIHT algorithm. The datapath is designed to have three stages as preprocessing, list generation and output stream. In the preprocessing stage, the flags which are supports the list generation stage are constituted. List of insignificant sets (LIS), list of insignificant pixels (LIP) and list of significant pixels (LSP) are formed in list generation stage. These lists contain the bit values which generate the output bit stream. The performance of the improved datapath design has been tested by compressing different images, and the obtained results are given. Cite this article as: Cekli S, Akman A. Enhanced SPIHT Algorithm with Pipelined Datapath Architecture Design. Electrica, 2019; 19(1): 29-36.

Energy Efficient and Side-Channel Secure Cryptographic Hardware for IoT-Edge Nodes

Design of ultralightweight but secure encryption engine is a key challenge for Internet-of-Things edge devices. This paper explores the system level design space for an ultralow power image sensor node for secure communication and proposes an optimized datapath architecture for 128-bit SIMON (SIMON128), a lightweight block cipher, for minimal performance, power, and area overheads with increased level of side-channel security. Various datapath architectures for SIMON are explored for simultaneously increasing energy-efficiency and resistance to power-based side-channel analysis (PSCA) attacks. Alternative datapath architectures are implemented on ASIC (15 nm CMOS) and field programmable gate array (FPGA) (Spartan-6, 45 nm) to perform power, performance, and area analysis. We show that, although a bitserial datapath minimizes area and power, a round unrolled datapath provides $80{\times }$ higher energy-efficiency and $143{\times }$ higher performance, compared to the baseline bitserial design. Moreover, the PSCA measurements performed using Sakura-G board with Spartan-6 FPGA, demonstrate that a 6-round unrolled datapath improves minimum-traces-to-disclosure for correlation power analysis (CPA) by at least $384{\times }$ over baseline bitserial design with no successful CPA even with 500 000 measurements. Finally, application to the image-sensor node demonstrates that optimized unrolled SIMON128 can provide equivalent performance to AES128 at lower area, higher energy efficiency, and improved side channel security.

Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP

AbstractConventional processor architectures are restricted in exploiting instruction level parallelism (ILP) due to the relatively low number of programmer-visible registers. Therefore, more recent processor architectures expose their datapaths so that the compiler (1) can schedule parallel instructions to different processing units and (2) can make effective use of local storage of the processing units. Among these architectures, the Synchronous Control Asynchronous Dataflow (SCAD) architecture is a new exposed datapath architecture whose processing units are equipped with first-in first-out (FIFO) buffers at their input and output ports.In contrast to register-based machines, the optimal code generation for SCAD is still a matter of research. In particular, SAT and SMT solvers were used to generate optimal resource constrained and optimal time constrained schedules for SCAD, respectively. As Answer Set Programming (ASP) offers better flexibility in handling such scheduling problems, we focus in this paper on using an answer set solver for both resource and time constrained optimal SCAD code generation. As a major benefit of using ASP, we are able to generatealloptimal schedules for a given program which allows one to study their properties. Furthermore, the experimental results of this paper demonstrate that the answer set solver can compete with SAT solvers and outperforms SMT solvers.This paper is under consideration for acceptance in TPLP.

Variable Length Instruction Compression on Transport Triggered Architectures

The memories used for embedded microprocessor devices consume a large portion of the system’s power. The power dissipation of the instruction memory can be reduced by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The memory-side power savings using compression are easily lost on inefficient fetch unit design. We propose an implementation for instruction template-based compression and two instruction fetch alternatives for variable length instruction encoding on transport triggered architecture, a static multiple-issue exposed data path architecture. With applications from the CHStone benchmark suite, the compression approach reaches an average compression ratio of 44% at best. We show that the variable length fetch designs reduce the number of memory accesses and often allow the use of a smaller memory component. The proposed compression scheme reduced the energy consumption of synthesized benchmark processors by 15% and area by 33% on average.