Datapath Architecture Research Articles

Power Optimization For A Datapath Of General Purpose Processor

This paper explores different data path architecture topologies for low power solutions. And we look at the energy optimization of different topologies. This paper is aimed at characterizing various architecture implementations of different data path operators like adders and multipliers and a different style of multiplier with minimum power and delay product and different adder topologies.

FPGAs, Programming Models, and Kit Cars

The degree of parallelism and ability to customize the RAM and data path architecture to the computation have enabled FPGAs to replace custom ASIC chips in many designs. Teams of highly skilled engineers crafting HDL code are the Formula-1 teams of the FPGA world, optimizing data paths from the thousands of programmable elements in an FPGA.

임베디드 병렬 프로세서를 위한 픽셀 서브워드 병렬처리 명령어 구현

프로세서 기술은 공정비용의 증가와 전력 소모 때문에 단순 동작 주파수를 높이는 방법이 아닌 다수의 프로세서를 집적하는 병렬 프로세싱 기술 발전이 이루어지고 있다. 본 논문에서는 멀티미디어에 내재한 무수한 데이터를 효과적으로 처리할 수 있는 SIMD(Single Instruction Multiple Data) 기반 병렬 프로세서를 소개하고, 또한 이러한 SIMD 기반 병렬 프로세서 아키텍처에서 이미지/비디오 픽셀을 효율적으로 처리 가능한 픽셀 서브워드 병렬처리 명령어를 제안한다. 제안하는 픽셀 서브워드 병렬처리 명령어는 48비트 데이터패스 아키텍처에서 4개의 12비트로 분할된 레지스터에 4개의 8비트 픽셀을 저장하고 동시에 처리함으로써 기존의 멀티미디어 전용 명령어에서 발생하는 오버플로우 및 이를 해결하기 위해 사용되는 패킹/언팽킹 수행의 상당한 오버헤드를 줄일 수 있다. 동일한 SIMD 기반 병렬 프로세서 아키텍처에서 모의 실험한 결과, 제안한 픽셀 서브워드 병렬처리 명령어는 baseline 프로그램보다 2.3배의 성능 향상을 보인 반면, 인텔사의 대표적인 멀티미디어 전용 명령어인 MMX 타입 명령어는 baseline 프로그램보다 단지 1.4배의 성능 향상을 보였다. 또한, 제안한 명령어는 baseline 프로그램보다 2.5배의 에너지 효율 향상을 보인 반면, MMX 타입 명령어는 baseline 프로그램보다 단지 1.8배의 에너지 효율 향상을 보였다. Processor technology is currently continued to parallel processing techniques, not by only increasing clock frequency of a single processor due to the high technology cost and power consumption. In this paper, a SIMD (Single Instruction Multiple Data) based parallel processor is introduced that efficiently processes massive data inherent in multimedia. In addition, this paper proposes pixel subword parallel processing instructions for the SIMD parallel processor architecture that efficiently operate on the image and video pixels. The proposed pixel subword parallel processing instructions store and process four 8-bit pixels on the partitioned four 12-bit registers in a 48-bit datapath architecture. This solves the overflow problem inherent in existing multimedia extensions and reduces the use of many packing/unpacking instructions. Experimental results using the same SIMD-based parallel processor architecture indicate that the proposed pixel subword parallel processing instructions achieve a speedup of <TEX>$2.3{\times}$</TEX> over the baseline SIMD array performance. This is in contrast to MMX-type instructions (a representative Intel multimedia extension), which achieve a speedup of only <TEX>$1.4{\times}$</TEX> over the same baseline SIMD array performance. In addition, the proposed instructions achieve <TEX>$2.5{\times}$</TEX> better energy efficiency than the baseline program, while MMX-type instructions achieve only <TEX>$1.8{\times}$</TEX> better energy efficiency than the baseline program.

Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN

An optimal implementation of 128-Pt FFT/IFFT for low power IEEE 802.15.3a WPAN using pseudo-parallel datapath structure is presented, where the 128-Pt FFT is devolved into 8-Pt and 16-Pt FFTs and then once again by devolving the 16-Pt FFT into 4×4 and 2×8. We analyze 128-Pt FFT/IFFT architecture for various pseudo-parallel 8-Pt and 16-Pt FFTs and an optimum datapath architecture is explored. It is suggested that there exists an optimum degree of parallelism for the given algorithm. The analysis demonstrated that with a modest increase in area one can achieve significant reduction in power. The proposed architectures complete one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 128-point FFT computation in less than 312.5 ns and thereby meet the standard specification. The relative merits and demerits of these architectures have been analyzed from the algorithm as well as implementation point of view. Detailed power analysis of each of the architectures with a different number of data paths at block level is described. We found that from power perspective the architecture with eight datapaths is optimum. The core power consumption with optimum case is 60.6 MW which is only less than half of the latest reported 128-point FFT design in 0.18u technology. Furthermore, a Single Event Upset (SEU) tolerant scheme for registers is also explored. The SEU tolerant scheme will not affect the performance, however, there is an increase power consumption of about 42 percent. Apart from the low power consumption, the advantages of the proposed architectures include reduced hardware complexity, regular data flow and simple counter based control.

High-Performance Optical-Flow Architecture Based on a Multi-Scale, Multi-Orientation Phase-Based Model

The accurate estimation of optical flow is a problem widely experienced in computer vision and researchers in this field are devoting their efforts to formulate reliable and robust algorithms for real life applications. These approaches need to be evaluated, especially in controlled scenarios. Because of their stability phase-based methods have generally been adopted in the various techniques developed to date, although it is still difficult to be sure of their viability in real-time systems due to their high requirements in terms of computational load. We describe here the implementation of a phase-based optical flow in a field-programmable gate array (FPGA) device. The system benefits from phase-information stability as well as sub-pixel accuracy without requiring additional computations and at the same time achieves high-performance computation by taking full advantage of the parallel processing resources of FPGA devices. Furthermore, the architecture extends the implementation to a multi-resolution and multi-orientation implementation, which enhances its accuracy and covers a wide range of detected velocities. Deep pipelined datapath architecture with superscalar computing units at different stages allows real-time processing beyond VGA image resolution. The final circuit is of significant complexity and useful for a wide range of fields requiring portable optical-flow processing engines.

Rate adaptation for energy efficiency in packet networks

Data networking services and applications enable substantial energy savings in broad sectors of economic activity by substituting the transportation of people and goods with the electronic transfer of data packets. To maximize the efficiency of packet networks, energy use in network equipment should scale rigorously with network traffic load. The two main frameworks for enforcing energy proportionality between energy consumption and network load are rate scaling and sleep state exploitation. Unfortunately, existing instantiations of these methods fail to scale energy consumption over the full load spectrum and require either tight coordination between adjacent nodes or new end-to-end traffic management mechanisms. In this paper, we define a novel approach for combining rate scaling and sleep state exploitation into a single rate adaptation scheme that preserves the best properties of its components in every portion of the load spectrum. We also demonstrate how rate adaptation can be applied to individual nodes by utilizing a simple data path architecture and show that rate adaptation is a feasible mechanism for achieving energy proportionality even when applied to individual systems or subsystems.

Full-chip characterization of compression algorithms for direct-write maskless lithography systems

Future lithography systems must produce more dense microchips with smaller feature sizes while maintaining throughput comparable to today's optical lithography systems. This places stringent data-handling requirements of up to 12 Tb/s on the design of any maskless lithography system. In past work, we have developed data-path architectures for such throughput and shown that lossless compression algorithms play a key role in such systems. We currently investigate the effectiveness of the Block C4 lossless layout compression algorithm in increasing throughput of direct-write maskless lithography systems. In particular, we characterize the compression efficiency of Block C4 on 1024×1024 blocks of select layers of two 65-nm chips: a state-of-the-art microprocessor chip and a low-density parity code chip used commonly in wireless communication applications. Overall, we have found that compression efficiency varies significantly from design to design, from layer to layer, and even within parts of the same layer. We propose a number of ways to cope with the variation of compression ratios within a layer and characterize the way each method affects the overall wafer layer throughput.

FPGA realization of a smart processing system for clinical diagnostic applications using pipelined datapath architectures

The paper describes the implementation of a novel smart data processing hardware system having medical diagnostic capabilities. The system is implemented in a FPGA chip for fast design cycle. The system employs a smart agent that can predict the future pathophysiological state of a patient using the past pathophysiological data and can thus predict the approaching critical condition of the patient before criticality actually occurs. This feature has been realized using fuzzy logic. In order to speed up the computation process, pipelined data processing architectures have been employed leading to a speed up of approximately three times. The whole system is realized on Altera Cyclone EP1K6Q240C8 FPGA chip requiring 5308 logic blocks. The system has been designed to be inexpensive, portable and user friendly for rural applications in developing countries.

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores

The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open research compiler infrastructure to a novel VLIW DSP (known as the PAC DSP core) and the specific design of code generation for its register file architecture. The PAC DSP utilizes port-restricted, distributed, and partitioned register file structures in addition to a heterogeneous clustered data-path architecture to attain low power consumption and a smaller die. As part of an effort to overcome the new challenges of code generation for the PAC DSP, we have developed a new register allocation scheme and other retargeting optimization phases that allow the effective generation of high quality code. Our preliminary experimental results indicate that our developed compiler can efficiently utilize the features of the specific register file architectures in the PAC DSP. Our experiences in designing compiler support for the PAC VLIW DSP with irregular resource constraints may also be of interest to those involved in developing compilers for similar architectures.

Instruction set synthesis with efficient instruction encoding for configurable processors

Application-specific instructions can significantly improve the performance, energy-efficiency, and code size of configurable processors. While generating new instructions from application-specific operation patterns has been a common way to improve the instruction set (IS) of a configurable processor, automating the design of ISs for given applications poses new challenges---how to create as well as utilize new instructions in a systematic manner, and how to choose the best set of application-specific instructions considering the various effects the new instructions may have on the data path and the compilation? To address these problems, we present a novel IS synthesis framework that optimizes the IS through an efficient instruction encoding for the given application as well as for the given data path architecture. We first build a library of new instructions created with various encoding alternatives taking into account the data path architecture constraints, and then select the best set of instructions while satisfying the instruction bitwidth constraint. We formulate the problem using integer linear programming and also present an effective heuristic algorithm. Experimental results using our technique generate ISs that show improvements of up to about 40% over the native IS for several application benchmarks running on typical embedded RISC processors.

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture

We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352 × 288) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8×3.1 mm2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 μW in a QCIF 15-fps sequence with one reference picture.

PipeRoute: a pipelining-aware router for reconfigurable architectures

We present a pipelining-aware router for fieldprogrammable gate arrays (FPGAs). The problem of routing pipelined signals is different from the conventional FPGA routing problem. The two-terminal N/sub D/ pipelined routing problem is to find the lowest cost route between a source and sink that goes through at least N (N/spl ges/1) distinct pipelining resources. In the case of a multiterminal pipelined signal, the problem is to find a minimum spanning tree (MST) that contains sufficient pipelining resources such that pipelining constraints at each sink are satisfied. In this paper, we first present an optimal algorithm for finding a lowest cost 1/sub D/ route. The optimal 1/sub D/ algorithm is then used as a building block for a greedy two-terminal N/sub D/ router. Next, we discuss the development of a multiterminal routing algorithm (PipeRoute) that effectively leverages both the 1/sub D/ and N/sub D/ routers. Finally, we present a preprocessing heuristic that enables the application of PipeRoute to pipelined FPGA architectures. PipeRoute's performance is evaluated by routing a set of benchmark netlists on the reconfigurable pipelined datapath (RaPiD) architecture. Our results show that the architecture overhead incurred in routing netlists on RaPiD is less than 20%. Further, the results indicate a possible trend between the architecture overhead and the percentage of pipelined signals in a netlist.

Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs

This paper presents the design of a soft IP for JPEG compression targeted for high performance in a FPGA device. The JPEG compressor architecture achieves high throughput with a deep and optimized pipeline and with a multiplierless datapath architecture. The JPEG compressor architecture was designed in a hierarchical and modular fashion and the details of the global architecture and of its modules are presented in this paper. A modular and strictly structural VHDL design is followed to develop the JPEG compressor soft IP. The VHDL codes were synthesized to Altera and Xilinx FPGAs. Synthesis results and relevant performance comparisons with related works are presented. Our high throughput compressor is able to compress 39.8 millions of pixels per second when mapped onto an Altera FLEX 10KE FPGA. Our JPEG soft IP mapped to FLEX 10KE low cost FPGA is able to compress 115 images per second in SDTV resolution (720 × 480 pixels). Considering this SDTV resolution our design is worthy as a core of an M-JPEG video compressor, reaching a real time processing rate of 30 fps, once mapped to the FLEX 10KE FPGA device.

Built-in sequential fault self-testing of array multipliers

Microprocessor datapath architectures operate on signed numbers usually represented in two's-complement or sign-magnitude formats. The multiplication operation is performed by optimized array multipliers of various architectures which are often produced by automatic module generators. Array multipliers have either a standard, nonrecoded signed (or unsigned) architecture or a recoded (modified Booth's algorithm) architecture. High-quality testing of array multipliers based on a comprehensive sequential fault model and not affecting their well-optimized structure has not been proposed in the past. In this paper, we present a built-in self-testing (BIST) architecture for signed and unsigned array multipliers with respect to a comprehensive sequential fault model. The BIST architecture does not alter the well-optimized multiplier structure. The proposed test sets can be applied externally but their regular nature makes them very suitable for embedded, self-test application by simple specialized hardware which imposes small overheads. Two different implementations of the BIST architecture are proposed. The first implementation focuses on the test invalidation problem and targets robust sequential fault testing, while the second one focuses on test cost reduction (test time and hardware overhead).

A High-Efficiency Strongly Self-Checking Asynchronous Datapath

This work examines the inherent self-checking (SC) property of latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic. Consequently, a highly efficient SC dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve SC. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.

A sub-mW MPEG-4 motion estimation processor core for mobile video application

This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a gradient descent search (GDS) algorithm that reduces required computational complexity to 15 MOPS. The GDS algorithm combined with a sub-block search method upgrades picture quality. The quality is almost equal to that of a full search method. An SIMD datapath architecture optimized for the algorithm decreases a clock frequency and supply voltage. A dedicated three-port SRAM macro for image data caches of the processor is newly designed to reduce power consumption. It has been fabricated with 0.18-/spl mu/m five-layer metal CMOS technology. The VLSI processing QCIF 15-f/s video consumes 0.4-mW power at 0.85-MHz clock frequency with 1.0-V supply voltage. It is applicable to mobile video applications.

Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs

Reed-Solomon (RS) coders are used for error-control coding in many applications such as digital audio, digital TV, software radio, CD players, and wireless and satellite communications. Traditionally, RS coders have been implemented using dedicated hardware. This paper considers software-based implementation of RS codecs. A hardware-software codesign approach is used to design the finite field datapath in a domain-specific digital signal processor (DSP) with low-energy RS codecs application in mind. These datapaths are designed to accommodate programmability with respect to the primitive polynomial as well as the field degree m. A novel heterogeneous digit-serial approach is proposed, where the heterogeneity corresponds to the use of different digit sizes in the multiply-accumulate (MAC) and degree reduction (DEGRED) subarrays. The salient feature of this digit-serial approach is that only the digit cells are implemented in hardware and the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations. Efficient scheduling strategies for digit-serial finite field multiplications are presented and applied to the design of low-energy high-performance RS codecs in software. Significant energy and energy-latency reductions can be achieved using the digit-serial datapaths, as compared with the traditional approach where a combined MAC-DEGRED (parallel multiplier) unit is used. It is concluded that for two-error-correcting RS(n, k) codes over finite field GF(2/sup 8/), datapath containing a parallel MAC unit (of digit size eight) and a DEGRED unit with digit size two (or four) leads to RS codecs with the least energy consumption and energy-latency products; with these datapath architectures and appropriate digit-serial scheduling strategies, more than 60% energy reduction and more than one-third energy-latency reduction can be achieved compared with the parallel multiplication datapath-based approach.

Design of VHDL-based totally self-checking finite-state machine and data-path descriptions

This paper presents a complete methodology to design a totally self-checking (TSC) sequential system based on the generic architecture of finite-state machine and data path (FSMD), such as the one deriving from VHDL specifications. The control part of the system is designed to be self-checking by adopting a state assignment providing a constant Hamming distance between each pair of binary codes. The design of the data path is based on both classical methodologies (e.g., parity, Berger code) and ad hoc strategies (e.g., multiplexer cycle) suited for the specific circuit structure. Self-checking properties and costs are evaluated on a set of benchmark FSM's and on a number of VHDL circuits.

Power estimation of digital data paths using HEAT

The major concerns of VLSI designers in the past were performance, area, reliability and cost. Power was only a secondary issue. In recent years, however, power, area, and speed have become equally important. There are many reasons for this new trend. Primarily, rapid advancement in semiconductor technology over the past decade has enabled designers to integrate many digital CMOS circuits on a single chip. However, the desirability of using these circuits in portable operations has necessitated the development of low-power technology. Portable applications range from desktop computers and audio-video based multimedia products to personal digital assistants and personal communicators. These systems demand both complex functionality and low power, which make their design challenging. The hierarchical energy analysis tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out.

A programmable 3.2-GOPS merged DRAM logic for video signal processing

This paper proposes a programmable high-performance architecture of datapath in the merged DRAM logic (MDL) for video signal processing. A model of a datapath in the programmable MDL is generated, and two basic parameters, total required clock cycles (TRCC) and DRAM access rate (DAR), are defined by analysis of the model. Design guidelines are suggested for the optimized video signal processor based on the modeling and analysis of the MDL. The inverse discrete cosine transform (IDCT) and motion compensation (MC) of the video signal processing are analyzed in the MDL architecture. Two measures, TRCC and DAR, are determined such that the data bandwidth between DRAM and logic is not a bottleneck in the MDL architecture. The efficient datapath is designed based on these design guidelines. The datapath has processing units (ALU, MAC, and barrel shifter) with splittabilities of data and multi-port SRAM. The maximum performance of the proposed datapath with 200-MHz clock frequency is 3.2 GOPS for 8-bit video signals, which can deal with a decoding high-level (1920/spl times/1080) in MPEG. The proposed MDL architecture has 2.1-4.8 times higher performance compared with conventional dedicated hardware chips. It can also be used for other multimedia signal processing due to its programmability.