Dataflow Architecture Research Articles

Exploring the potential of heterogeneous von neumann/dataflow execution models

General purpose processors (GPPs), from small inorder designs to many-issue out-of-order, incur large power overheads which must be addressed for future technology generations. Major sources of overhead include structures which dynamically extract the data-dependence graph or maintain precise state. Considering irregular workloads, current specialization approaches either heavily curtail performance, or provide simply too little benefit. Interestingly, well known explicit-dataflow architectures eliminate these overheads by directly executing the data-dependence graph and eschewing instruction-precise recoverability. However, even after decades of research, dataflow architectures have yet to come into prominence as a solution. We attribute this to a lack of effective control speculation and the latency overhead of explicit communication, which is crippling for certain codes. This paper makes the observation that if both out-of-order and explicit-dataflow were available in one processor, many types of GPP cores can benefit from dynamically switching during certain phases of an application's lifetime. Analysis reveals that an ideal explicit-dataflow engine could be profitable for more than half of instructions, providing significant performance and energy improvements. The challenge is to achieve these benefits without introducing excess hardware complexity. To this end, we propose the Specialization Engine for Explicit-Dataflow (SEED). Integrated with an inorder core, we see 1.67× performance and 1.65× energy benefits, with an Out-Of-Order (OOO) dual-issue core we see 1.33× and 1.70×, and with a quad-issue OOO, 1.14× and 1.54×.

A Hash Table for Line-Rate Data Processing

FPGA-based data processing is becoming increasingly relevant in data centers, as the transformation of existing applications into dataflow architectures can bring significant throughput and power benefits. Furthermore, a tighter integration of computing and network is appealing, as it overcomes traditional bottlenecks between CPUs and network interfaces, and dramatically reduces latency. In this article, we present the design of a novel hash table, a fundamental building block used in many applications, to enable data processing on FPGAs close to the network. We present a fully pipelined design capable of sustaining consistent 10Gbps line-rate processing by deploying a concurrent mechanism to handle hash collisions. We address additional design challenges such as support for a broad range of key sizes without stalling the pipeline through careful matching of lookup time with packet reception time. Finally, the design is based on a scalable architecture that can be easily parameterized to work with different memory types operating at different access speeds and latencies. We have tested the proposed hash table in an FPGA-based memcached appliance implementing a main-memory key-value store in hardware. The hash table is used to index 2 million entries in 24GB of external DDR3 DRAM while sustaining 13 million requests per second, the maximum packet rate that can be achieved with UDP packets on a 10Gbps link for this application.

Conceptual Design of 3-D FDTD Dedicated Computer With Dataflow Architecture for High Performance Microwave Simulation

For practical use of microwave simulations in industry applications such as high frequency product design, this paper presents a conceptual design of 3-D finite difference time domain (FDTD) dedicated computer with dataflow architecture as one of the portable high performance computing technologies. A basic concept of the dataflow architecture for the FDTD dedicated computer itself was presented already in 2003 for 2-D microwave simulations. Detail design of 3-D FDTD dataflow machine is considered in this paper.

Gram–Schmidt Process in Different Parallel Platforms

Important operations in numerical computing are vector orthogonalization. One of the well-known algorithms for vector orthogonalisation is Gram–Schmidt algorithm. This is a method for constructing a set of orthogonal vectors in an inner product space, most commonly the Euclidean space Rn. This process takes a finite, linearly independent set S = {b1, b2, …, bk} vectors for k = n and generates an orthogonal set S1 = {o1, o2, …, ok}. Like the most of the dense operations and big data processing problems, the Gram–Schmidt process steps can be performed by using parallel algorithms and can be implemented in parallel programming platforms. The parallelized algorithm is dependent to the platform used and needs to be adapted for the optimum performance for each parallel platform. The paper shows the algorithms and the implementation process of the Gram –Schmidt vector orthogonalosation in three different parallel platforms. The three platforms are: a) control flow shared memory hardware systems with OpenMP, b) control flow distributed memory hardware systems with MPI and c) dataflow architecture systems using Maxeler Data Flow Engines hardware. Using as single running example a parallel implementation of the computation of the Gram –Schmidt vector orthogonalosation, this paper describes how the fundamentals of parallel programming, are dealt in these platforms. The paper puts into evidence the Maxeler implementation of the Gram–Schmidt algorithms compare to the traditional platforms. Paper treats the speedup and the overall performance of the three platforms versus sequential execution for 50-dimensional Euclidian space.

Data flow control paradigm and its graphical representation in system oriented architectures

A method of representing the architecture of information systems using a data flow paradigm is given in the paper. A graphical form of representing the operation of information systems is worked out. It can clearly and effectively describe complex interactions between components of the SOA systems in a convenient and simple way. An XML format of describing the data flow architecture in SOA is developed. A method of compiling this representation in OOP languages is proposed. The possibility of generating a parallel-executable code and organizing a unit testing system by means of applying graphic description is considered. The proposed method of graphic description of SOA-based information systems, unlike UML diagrams allows compiling into an executable parallel code. As a result of the studies, the methodology of graphic description of cycles and recursions in data flow systems, oriented onto SOA systems, is defined. The method of graphic description of the data flow validation process is developed. The practical application of such method of describing architecture can be carried out along with various programming languages and can effectively solve problems in the field of enterprise information systems using a service-oriented architecture, image processing, analysis of high-volume data, and control systems.

Carrying on the legacy of imperative languages in the future parallel computing era

Abstract There has been a renewed interest in dataflow computing models in recent years of technology scaling. Potentiality of exploiting huge parallelism, with the expense of low power, simpler circuit, less silicon area, is the main characteristic of a dataflow model. Growing trends in housing large number of functional units in a single chip, making use of local clocks, reducing energy consumptions, avoiding global wires are the main reasons behind the resurgence of dataflow models. To program a dataflow machine, new architectures suggest imperative languages rather than functional type dataflow languages or parallel languages because this is the right way to make the new architectures popular among the general community. Although for several decades scientists have been working on how imperative languages can be used in dataflow models efficiently, there is no systematic review on those works. Existing reviews on dataflow paradigm mainly focus on the architectures. Although few papers review programming languages of dataflow architectures, their discussions are limited to only dataflow languages and visual programming languages which are fundamentally different from imperative languages. In this paper, we conduct a systematic review on those works that attempt to provide a way to use imperative languages in any type of dataflow architectures. Our survey of compilers and related architectures cover the aspects like translation mechanisms of program construct, their optimization techniques, memory ordering methods, program allocation and scheduling and special architectural features. We also present some of our observations and future research directions obtained by exploring the literature.

Mikroprogram pre riadenie procesu spájania operandov v architektúre DF KPI

V článku uvedená architektúra je založená na výpočtovom modeli "data flow", v ktorom riadenie výpočtu je založené na spracovaní toku dát. Základným prvkom DF architektúry je koordinačný procesor (CP), ktorý je zodpovedný za riadenie a organizáciu vykonávania inštrukcií. Štruktúrna organizácia CP je navrhnutá ako dynamický multifunkčný systém. Pri vykonávaní operácií môže CP prechádzať rôznymi stavmi, v dôsledku čoho táto jednotka predstavuje dynamický prúdový systém. Prechod a poradie prechodu medzi jednotlivými stavmi CP je podmienený typom spracovaného operátora pri interpretovaní prúdu operandov. Z možných typov operátorov, článok uvádza mikroprogramové riadenie pre jednovstupové operátory.

Innovative Operating Memory Architecture for Computers using the Data Driven Computation Model

This paper deals with the data flow computing paradigm, with the characteristics of program execution control using a flow of data instead of a flow of instructions. Data flow computing represents an important alternative to the control flow computing paradigm, which is currently the mainstream computing paradigm represented by architectures mostly based on the Von Neumann principles, in which the flow of program execution is controlled by a flow of instructions. This paper also deals with the tile computing paradigm - a modern approach to designing multi-core microprocessors with components laid out in two-dimensional grids with various geometries of cores, memory elements and interconnection networks with architectures using both data flow and control flow program execution control. In this paper we introduce a data flow computer architecture designed at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Kosice, Slovakia, employing the principles of tile computing. Efficient data flow architectures applying a different approach to the control of program execution flow also demand a different operating memory design. As the part of our effort to build data flow computer architectures, we have designed an innovative memory architecture that fulfils the specific needs of data flow computer architectures. In the final section of the paper we describe the functions and operations possible with this kind of memory.

Multiverse Data-Flow Control

In this paper, we present a data-flow system which supports comparative analysis of time-dependent data and interactive simulation steering. The system creates data on-the-fly to allow for the exploration of different parameters and the investigation of multiple scenarios. Existing data-flow architectures provide no generic approach to handle modules that perform complex temporal processing such as particle tracing or statistical analysis over time. Moreover, there is no solution to create and manage module data, which is associated with alternative scenarios. Our solution is based on generic data-flow algorithms to automate this process, enabling elaborate data-flow procedures, such as simulation, temporal integration or data aggregation over many time steps in many worlds. To hide the complexity from the user, we extend the World Lines interaction techniques to control the novel data-flow architecture. The concept of multiple, special-purpose cursors is introduced to let users intuitively navigate through time and alternative scenarios. Users specify only what they want to see, the decision which data are required is handled automatically. The concepts are explained by taking the example of the simulation and analysis of material transport in levee-breach scenarios. To strengthen the general applicability, we demonstrate the investigation of vortices in an offline-simulated dam-break data set.

A novel reconfigurable data-flow architecture for real time video processing

This paper describes a dynamically reconfigurable data-flow hardware architecture optimized for the computation of image and video. It is a scalable hierarchically organized parallel architecture that consists of data-flow clusters and finite-state machine (FSM) controllers. Each cluster contains various kinds of cells that are optimized for video processing. Furthermore, to facilitate the design process, we provide a C-like language for design specification and associated design tools. Some video applications have been implemented in the architecture to demonstrate the applicability and flexibility of the architecture. Experimental results show that the architecture, along with its video applications, can be used in many real-time video processing.

An AES chip with DPA resistance using hardware-based random order execution

This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm2. A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance.

Service Oriented Paradigm for Massive Multiplayer Online Games

In recent times Massive Multiplayer Online Game has appeared as a computer game that enables hundreds of players from all parts of the world to interact in a game world (common platform) at the same time instance. Current architecture used for MMOGs based on the classic tightly coupled distributed system. While, MMOGs are getting more interactive same time number of interacting users is increasing, classic implementation architecture may raise scalability and interdependence issues. This requires a loosely coupled service oriented architecture to support evolution in MMOG application. Data flow architecture, Event driven architecture and client server architecture are basic date orchestration approaches used by any service oriented architecture. Real time service is hottest issue for service oriented architecture. The basic requirement of any real time service oriented architecture is to ensure the quality of service. In this paper we have proposed a service oriented architecture for massive multiplayer online game and a specific middleware (based on open source DDS) in MMOGs for fulfilling real time constraints.

HyperFlow and ITK v4 Integration: Exploring the use of a modern parallel dataflow architecture in ITK

In this document, we report our activities on the subcontract with Kitware where we carefully study the upcoming ITK v4 pipeline design to help the ITK v4 development team to add support of modern dataflow architectures to ITK.

A Compiler for Ladder Diagram to Multi-Core Dataflow Architecture

Multi-core and dataflow architecture recently researched on parallel computing can well satisfy the requirement of high-performance for PLC processors handling program by exploiting parallelism in the program. But the compiler translating the ladder diagram program into the instructions of the architecture has not been yet developed. For the problem, the paper presents a compiler aiming at editing a ladder diagram which is one of programming languages of PLC and then compiling it into instructions of multi-core function-level dataflow architecture. The compiler takes row doubly linked list as internal representation of a ladder diagram, and logic binary tree as intermediate representation during the process of compiling according to similarity of the binary tree to function-level dataflow graph, written in java.

GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors

The past two decades have witnessed a revolution in the use of electronic devices in our daily activities. Increasingly, such activities involve the exchange of personal and sensitive data by means of portable and light weight devices. This implied the use of security applications in devices with tight processing capability and low power budget. Current architectures for processors that run security applications are optimized for either high-performance or low energy consumption. We propose an implementation for an architecture that not only provides high performance and low energy consumption but also mitigates security attacks on the cryptographic algorithms which are running on it. The proposed architecture of the Globally-Asynchronous Locally-Synchronous-based Low Power Security Processor (GALS-based LPSP) inherits the scheduling freedom and high performance from the dataflow architectures and the low energy consumption and flexibility from the GALS systems. In this paper, a prototype of the GALS-based LPSP is implemented as a soft core on the Virtex-5 (xc5-vlx155t) FPGA. The architectural features that allow the processor to mitigate Side-Channel attacks are explained in detail and tested on the current encryption standard, the AES. The performance analysis reveals that the GALS-based LPSP achieves two times higher throughput with one and a half times less energy consumption than the currently used embedded processors.

On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling

With growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core Dynamic Voltage and Frequency scaling (DVFS) is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real Multiple Input Multiple Output (MIMO) Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved.

Double Input Operators of the DF KPI System

Dataflow architectures can be used advantageously for computation-oriented applications that exhibit a fine grain parallelism. The implementation of the dataflow computer architecture depends on the form of execution of the dataflow program instructions, which is implemented as a process of receiving, processing and transmission of data tokens. The architecture described in this paper belongs to a class of dynamic dataflow architectures with direct operand matching. The concept of direct operand matching represents the elimination of the costly process (in terms of computing time) related to associative searching of the operands. This process is associated with the processing units of the proposed system. The processing units are designed as a dynamic multifunction pipelined unit of five segments, Load-Fetch-Operate-Matching-Copy. This pipeline stages handle processing of operand matching of dataflow operators. From the many types of operators, this paper describes microprogram managing for double input operators.

PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model

This work proposes and implements a reconfigurable parallel architecture based on dataflow for numerical computation, named PRADA. This architecture uses concepts of parallel processing to obtain a scalable performance and the dataflow concept for controlling the parallel execution of instructions. PRADA is composed by a control unit and several processing elements (PEs). In the control unit, there are several functional blocks, including data and instruction memories. Each PE is composed by an ALU and buffers. PRADA is organised as a cluster, in which several independent dataflow modules are interconnected together. PRADA was developed in VHDL and implemented in reconfigurable hardware using a FPGA device. Therefore, it can offer high performance, scalability and customised solutions for engineering problems. Results of the application of PRADA to the computation of a digital filter and a cryptography algorithm are presented. Results are also compared with other different architectures, such as microprocessors, ASICs, DSPs, reconfigurable architectures and dataflow architectures. In most cases, PRADA achieved either competitive or higher performance than the other architectures, regarding the measures used. Overall results suggest that this architecture can be applied to several classes of problems that may require a high throughput, such as cryptography, optimisation and scientific computing.

Neutron Sensitivity of High-Speed Networks

Recently, engineers have been studying on-payload networks for fast communication paths. Using intrasystem networks as a means to connect devices together allows for a flexible payload design that does not rely on dedicated communication paths between devices. In this manner, the data flow architecture of the system can be dynamically reconfigured to allow data routes to be optimized for the application or configured to route around devices that are temporarily or permanently unavailable. To use intrasystem networks, devices will need network controllers and switches. These devices are likely to be affected by single-event effects, which could affect data communication. In this paper, we will present radiation data and performance analysis for using a Broadcom network controller in a neutron environment.

Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

In this paper a dataflow architecture is introduced that maps efficiently onto multi-FPGA platforms and is composed of communication channels which can be dynamically adapted to the dataflow of the algorithm. The reconfiguration of the topology can be accomplished within a single clock cycle while DSP operations are in progress. Finally, the programmability and scalability of the proposed architecture is demonstrated by a high-performance parallel FFT implementation.