Dataflow Actors Research Articles

Automated level-based clustering of dataflow actors for controlled scheduling complexity

Dataflow Models of Computation (MoCs) significantly enhance parallel computing by efficiently expressing application parallelism on multicore architectures, unlocking greater performance and throughput. However, the complexity of graphs within dataflow-based systems can result in a time-consuming resource allocation process. To address this issue, a solution is to cluster computations to ease heuristic solving. The information encompassing the context of computations and the constraints of the architecture plays a crucial role in determining application performance. This paper presents an automated approach that leverages this information to control graph complexity prior to the resource allocation process. Experiments demonstrate that the proposed method, driven by clustering, not only yields improved throughput but also provides better mapping decisions and data transfer efficiency, achieving a throughput up to 1.8 times higher than state-of-the-art techniques.

Run-Time Remapping Algorithm of Dataflow Actors on NoC-Based Heterogeneous MPSoCs

Multiprocessor system-on-chip (MPSoC) platforms have been emerging as the main solution to cope with processor frequency ceiling and power density issues while still improving performances. Then, network-on-chip (NoC) has been adopted to provide the increasing number of processors with the required communication bandwidth as well as with the necessary flexibility. Video processing and streaming applications are adopting dynamic dataflow model of computation as the need for high performance parallel computing is growing. Dataflow applications executed on modern MPSoC-based architectures are becoming increasingly dynamic and more data-dependent. Different tasks execute concurrently with significant modifications in their workloads and resource demanding over time depending on the input data. Hence, adopting any static or offline dynamic scheduling for mapping tasks will not cope with the computation variations. This article introduces an original run-time mapping algorithm based on the Move Based (MB) method targeting a dedicated heterogeneous NoC-based MPSoC architecture to achieve workload balancing and optimized communication traffic. The performance of the proposed algorithm is verified by conducting cycle-accurate SystemC simulations of the adopted NoC implementing a real MPEG4-SP decoder. The obtained results reveal the effectiveness of our proposed algorithm. For various real-life videos, the proposed algorithm systematically succeeded to enhance significantly the performance.

Verifying parallel dataflow transformations with model checking and its application to FPGAs

Abstract Dataflow languages are widely used for programming real-time embedded systems. They offer high level abstraction above hardware, and are amenable to program analysis and optimisation. This paper addresses the challenge of verifying parallel program transformations in the context of dynamic dataflow models, where the scheduling behaviour and the amount of data each actor computes may depend on values only known at runtime. We present a Linear Temporal Logic (LTL) model checking approach to verify a dataflow program transformation, using three LTL properties to identify cyclostatic actors in dynamic dataflow programs. The workflow abstracts dataflow actor code to Fiacre specifications to search for counterexamples of the LTL properties using the Tina model checker. We also present a new refactoring tool for the Orcc dataflow programming environment, which applies the parallelising transformation to cyclostatic actors. Parallel refactoring using verified transformations speedily improves FPGA performance, e.g.15.4 × speedup with 16 actors.

Development of an Automatic Dependent Surveillance Broadcast Modem Using Dataflow Specifications

Air traffic control nowadays mainly relies on radar based surveillance system and with the growth of air traffic, the problems of air transportation system is approaching its limit. The increase in the task of scheduling flights results in higher overall operation cost and pose higher rate of flight safety hazards. Thus, an upgrade from conventional air traffic management systems to the Next Generation Air Transportation (NextGen) System is required. The Automatic Dependent Surveillance Broadcast (ADS-B) modem is the key component of NextGen, which uses Global Navigation Satellite System (GNSS) to provide better accuracy of aircraft position. ADS-B continuously broadcasts information on altitude, position, identity, velocity, and other aircraft information to generate best picture for air traffic management. In this paper, the ADS-B modulator and demodulator have been developed using high-level RVC-CAL dataflow actor language, and automatically synthesized to C and Verilog/VHDL codes for hardware and software implementations. Results show that the performance of the proposed designs at high-level exceeds the minimum throughput requirement specified in the ADS-B standard by a factor of more than three.

A New Static Data Flow Clustering Algorithm for Task Scheduling of Irregular Mesh in NoCs Based on Complex Networks

The majority of recent embedded systems are based on MPSoCs (Multi-Processors System on Chip) architectures. The topologies and the interconnections inside multi processors almost adopt NoCs (Networks on Chip) whose topology and task scheduling algorithm have a direct impact on its performances. In this paper, by using static data flow, a task scheduling algorithm which would automatically assign the application tasks onto different processors is proposed based on complex network. The goal of our algorithm is to replace the static data flow subnetwork by a single dynamic data flow actor such that the global performance in terms of latency and throughput is optimized. Through complex network, it greatly enhances the power of our algorithm in terms of avoiding deadlock, saving energy and providing for integration with more general models of computation. Experimental results show up to 60% performance improvement for real-world examples.

Move Based Algorithm for Runtime Mapping of Dataflow Actors on Heterogeneous MPSoCs

Considering the evolution towards highly variable data flow applications based on an increasing impact of dynamic actors, we must target at runtime the best matching between dataflow graphs and heterogeneous multiprocessor platforms. Thus the mapping must be dynamically adapted depending on data and on communication loads between the computation cores. This is typically the case for mobile devices that run multimedia applications. The problem of mapping a dataflow application, e.g. a network of computational actors, on a multiprocessor platform can be modeled as a problem of partitioning where the cells are the dataflow actors and the partitions are the processors. While the benefit of executing a computational part by one processor rather than another one is usually well shown, the migration overhead is also usually not considered. This paper presents a dynamic mapping algorithm that is performed at runtime, based on a single-move possibility that jointly considers the cost and benefit of possible migrations. The method is first applied on a set of randomly generated benchmarks with different features and different scenarios. Then it is applied to a MPEG4 simple profile video decoder with different input sequences. The results systematically show that the runtime mapping significantly improves the initial mapping. It is fast enough to be executed at runtime in order to track the best mapping according to data variations. The other observation is that not considering the migration cost of the new mapping could lead to worst performance than the original one.

Actor Merging for Dataflow Process Networks

Dataflow process networks provide a versatile model of computation for specifying signal processing applications in a platform independent fashion. This attractive feature of dataflow has lately been realized in dataflow programming tools that allow synthesizing the same application specification as both fixed hardware circuits and as software for programmable processors. However, in practice, the specification granularity of the dataflow program remains an arbitrary choice of the designer. Dataflow specifications of the same application with equivalent I/O behaviour can range from a single dataflow actor to a very fine grained network composed of elementary processing operations. A very fine grained dataflow specification might result into a high performance implementation when synthesized as hardware, but might perform poorly when executed on a programmable processor. This article presents actor merging as one solution for this performance portability problem of dataflow programs. In contrast to previous work around actor merging, this article presents a methodology that can merge also dynamic dataflow actors. To support these claims, results of experiments on several processing platforms and application examples ranging from telecommunications to video compression are reported.

High-level dataflow programming for real-time image processing on smart cameras

We describe the application of the caph programming language to the implementation of complex real-time image processing application on a FPGA embedded in a smart camera architecture. caph is based upon the dataflow model of computation. Applications are described as networks of purely dataflow actors exchanging tokens through unidirectional channels and the behavior of each actor is defined as a set of transition rules using pattern matching. We show that this model is naturally suited to the description of applications operating on the fly on digital video streams and supports a fully automated compilation path producing efficient VHDL code. This is demonstrated on an application performing the extraction of HOG (histogram of oriented gradient) feature vectors in real time on the dreamcam smart camera, an experimental platform developed at our institute.

Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing

Parallelization of Digital Signal Processing (DSP) software is an important trend in Multiprocessor System-on-Chip (MPSoC) implementation. The performance of DSP systems composed of parallelized computations depends on the scheduling technique, which must in general allocate computation and communication resources for competing tasks, and ensure that data dependencies are satisfied. In this paper, we formulate a new type of parallel task scheduling problem called Parallel Actor Scheduling (PAS) for MPSoC mapping of DSP systems that are represented as Synchronous Dataflow (SDF) graphs. In contrast to traditional SDF-based scheduling techniques, which focus on exploiting graph level (inter-actor) parallelism, the PAS problem targets the integrated exploitation of both intra- and inter-actor parallelism for platforms in which individual actors can be parallelized across multiple processing units. We first address a special case of the PAS problem in which all of the actors in the DSP application or subsystem being optimized are parallel actors (i.e., they can be parallelized to exploit multiple cores). For this special case, we develop and experimentally evaluate a two-phase scheduling framework with three work flows that involve particle swarm optimization (PSO) -- PSO with a mixed integer programming formulation, PSO with simulated annealing, and PSO with a fast heuristic based on list scheduling. Then, we extend our scheduling framework to support the general PAS problem, which considers both parallel actors and sequential actors (actors that cannot be parallelized) in an integrated manner. We demonstrate that our PAS-targeted scheduling framework provides a useful range of trade-offs between synthesis time requirements and the quality of the derived solutions. We also demonstrate the performance of our scheduling framework from two aspects: simulations on a diverse set of randomly generated SDF graphs, and implementations of an image processing application and a software defined radio benchmark on a state-of-the-art multicore DSP platform.

A DSP-Based HEVC decoder implementation using an actor language dataflow model

During the last decades, new video compression standards arose every few years with always higher compression gains and considerable increases on the computational cost. Single core processors have reached their limit and multicore processors are there to overcome this issue to give more processing power. In order to accelerate the implementation of new video coding standards, MPEG has standardized an alternative framework to describe video decoders. It is based on reference decoders written in the RVC CAL dataflow actor language. From these descriptions, a compiler - Open RVC CAL compiler (Orcc) - allows the automatic generation of C code dedicated to the target processor. In this paper, a DSP based decoder compliant with the new High Efficiency Video Coding (HEVC) standard has been implemented using a CAL RVC model as a starting point. This is the first implementation of an HEVC decoder with DSP technology based on a HEVC RVC CAL model. The decoder has been compared in performance with a GPP implementation, also based on the RVC CAL model, and outperforms it by more than 50%. Additionally, the performance of this decoder is compared with that of other DSP-based HEVC decoders implemented without using the Orcc infrastructure1.

A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs

In this article, an efficient rule-based clustering algorithm for static dataflow subgraphs in a dynamic dataflow graph is presented. The clustered static dataflow actors are quasi-statically scheduled , in such a way that the global performance in terms of latency and throughput is improved compared to a dynamically scheduled execution, while avoiding the introduction of deadlocks as generated by naive static scheduling approaches. The presented clustering algorithm outperforms previously published approaches by a faster computation and more compact representation of the derived quasi-static schedule. This is achieved by a rule-based approach, which avoids an explicit enumeration of the state space. A formal proof of the correctness of the presented clustering approach is given. Experimental results show significant improvements in both, performance and code size, compared to a state-of-the-art clustering algorithm.

Classification of Dataflow Actors with Satisfiability and Abstract Interpretation

Dataflow programming has been used to describe signal processing applications for many years, traditionally with cyclo-static dataflow (CSDF) or synchronous dataflow (SDF) models that restrict expressive power in favor of compile-time analysis and predictability. More recently, dynamic dataflow is being used for the description of multimedia video standards as promoted by the RVC standard (ISO/IEC 23001:4). Dynamic dataflow is not restricted with respect to expressive power, but it does require runtime scheduling in the general case, which may be costly to perform on software. The authors presented in a previous paper a method to automatically classify actors of a dynamic dataflow program within more restrictive dataflow models when possible, along with a method to transform the actors classified as static to improve execution speed by reducing the number of FIFO accesses (Wipliez & Raulet, 2010). This paper presents an extension of the classification method using satisfiability solving, and details the precise semantics used for the abstract interpretation of actors. The extended classification is able to classify more actors than what could previously be achieved.

Analysis of SystemC actor networks for efficient synthesis

Applications in the signal processing domain are often modeled by dataflow graphs. Due to heterogeneous complexity requirements, these graphs contain both dynamic and static dataflow actors. In previous work, we presented a generalized clustering approach for these heterogeneous dataflow graphs in the presence of unbounded buffers. This clustering approach allows the application of static scheduling methodologies for static parts of an application during embedded software generation for multiprocessor systems. It systematically exploits the predictability and efficiency of the static dataflow model to obtain latency and throughput improvements. In this article, we present a generalization of this clustering technique to dataflow graphs with bounded buffers, therefore enabling synthesis for embedded systems without dynamic memory allocation. Furthermore, a case study is given to demonstrate the performance benefits of the approach.

Dataflow process networks

We review a model of computation used in industrial practice in signal processing software environments and experimentally and other contexts. We give this model the name process and study its formal properties as well as its utility as a basis for programming language design. Variants of this model are used in commercial visual programming systems such as SPW from the Alta Group of Cadence (formerly Comdisco Systems), COSSAP from Synopsys (formerly Cadis), the DSP Station from Mentor Graphics, and Hypersignal from Hyperception. They are also used in research software such as Khoros from the University of New Mexico and Ptolemy from the University of California at Berkeley, among many others. Dataflow process networks are shown to be a special case of Kahn process networks, a model of computation where a number of concurrent processes communicate through unidirectional FIFO channels, where writes to the channel are nonblocking, and reads are blocking. In dataflow process networks, each process consists of repeated firings of a dataflow actor. An actor defines a (often functional) quantum of computation. By dividing processes into actor firings, the considerable overhead of context switching incurred in most implementations of Kahn process networks is avoided. We relate dataflow process networks to other dataflow models, including those used in dataflow machines, such as static dataflow and the tagged-token model. We also relate dataflow process networks to functional languages such as Haskell, and show that modern language concepts such as higher-order functions and polymorphism can be used effectively in dataflow process networks. A number of programming examples using a visual syntax are given. >

OR-parallel evaluation of logic programs on a multi-ring dataflow machine

Logic programming languages have gained wide acceptance because of two reasons. First is their clear declarative semantics and the second is the wide scope for parallelism they provide which can be exploited by building suitable parallel architectures. In this paper, we propose a multi-ring dataflow machine to support theOR-parallelism and theArgument parallelism of logic programs. A new scheme is suggested for handling the deferred read mechanism of the dataflow architecture. The required data structures, the dataflow actors and the builtin dataflow procedures for OR-parallel execution are discussed. Multiple binding environments arising in the OR-parallel execution are handled by a new scheme called thetagged variable scheme. Schemes for constrained OR-parallel execution are also discussed.

Performance evaluation of a simulated data-flow computer with low-resolution actors

In the ambition to go beyond a single-processor architecture, to enhance programmability, and to take advantage of the power brought by VLSI devices, data-flow systems and languages were devised. Indeed, due to their functional semantics, these languages offer promise in the area of multiprocessor systems design and will possibly enable the development of computers comprising large numbers of processors with a corresponding increase in performance. Several important design problems have to be surmounted and are described here. We thus present a “variable-resolution” scheme, where the level of primitives can be selected so that the overhead due to the data-flow mode of operation is reduced. A deterministic simulation of a data-flow machine with a variable number of processing elements was undertaken and is described here. The tests were performed using various program structures such as directed acyclic graphs, vector operations, and array handling. The performance results observed confirm the advantage of actors with variable size and indicate the presence of a trade-off between overhead control and the need to control parallelism in the program. We also look at some of the communication issues and examine the effect of several interconnection networks (dual counter-rotating rings, daisy chain, and optimal double loop network) on the performance. It is shown how increasing communication costs induce a performance degradation that can be masked when the size of the basic data-flow actor is increased. The asociative memory cycle time is also changed with similar conclusions. Finally, the lower-resolution scheme is applied to the array handling case; the observations confirm the advantage of a more complex actor at the array level.