Abstract
Abstract Dataflow languages are widely used for programming real-time embedded systems. They offer high level abstraction above hardware, and are amenable to program analysis and optimisation. This paper addresses the challenge of verifying parallel program transformations in the context of dynamic dataflow models, where the scheduling behaviour and the amount of data each actor computes may depend on values only known at runtime. We present a Linear Temporal Logic (LTL) model checking approach to verify a dataflow program transformation, using three LTL properties to identify cyclostatic actors in dynamic dataflow programs. The workflow abstracts dataflow actor code to Fiacre specifications to search for counterexamples of the LTL properties using the Tina model checker. We also present a new refactoring tool for the Orcc dataflow programming environment, which applies the parallelising transformation to cyclostatic actors. Parallel refactoring using verified transformations speedily improves FPGA performance, e.g.15.4 × speedup with 16 actors.
Highlights
In the dataflow model of execution, the firing of actors depends only on data availability, allowing each actor in a program to execute asynchronously without a global control flow sequentialising their execution.Dataflow languages are a natural abstraction for FPGAs, since a program’s dataflow structure is distributed across the programmable hardware fabric
block RAM (BRAM) are distributed across FPGA fabric, meaning there is no memory contention when multiple actors update their kernel variables, e.g. intermediate arrays
The dataflow programming model can be exploited for high FPGA performance, e.g. [1], or as an Intermediate Representation in compilers for higher level FPGA languages e.g. [2]
Summary
In the dataflow model of execution, the firing of actors depends only on data availability, allowing each actor in a program to execute asynchronously without a global control flow sequentialising their execution.Dataflow languages are a natural abstraction for FPGAs, since a program’s dataflow structure is distributed across the programmable hardware fabric. BRAMs are distributed across FPGA fabric, meaning there is no memory contention when multiple actors update their kernel variables, e.g. intermediate arrays That is, both computation and memory access is inherently parallel. Software languages often support spawning new tasks/actors at runtime across threads on a multicore CPU This is unsuitable when compiling programs to programmable hardware (i.e. application specific circuits), where the fixed task graph is mapped into the hardware with place and route, and cannot be changed without re-synthesis. Dataflow programming models offer a more explicit way to express independent parallel tasks, and which tasks communicate They clearly separate computation and communication, and are popular for embedded systems programming, especially FPGAs, where the entire task graph and communication routing must be fixed in hardware prior to execution
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