Data Conversion Circuits Research Articles

A 256 × 256 CMOS image sensor with differential readout and data converter circuits

SummaryIn this paper, a 256 × 256 CMOS image sensor is introduced in which the pixel signals are read and converted into digital data in a completely differential mode. This technique helps to obtain pixel signals with higher linearity and accuracy compared with conventional methods. Improving the linearity and accuracy of the image sensor has a direct impact on increasing the quality of the generated images. The simulation results of the proposed pixel readout circuit show that the THD, SINAD, SNR, and SFDR are 0.45%, 47 dB, 66 dB, and 46 dB, respectively. The voltage gain of the proposed readout circuit is about 1, causing it to read the photodetector signals more accurately than the conventional methods. A full differential single‐slope ADC with a working frequency of 50 Mhz has the task of converting the pixel signal to 10 bits of digital data. The total power consumption of a column of sensors is about 80 μW. All the circuits are designed and implemented using 0.18‐μm CMOS technology in Virtuoso and simulated by the SPECTRE.

Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology

<p><span>Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.</span></p>

An adaptive calibration technique for thermistor with varying temperature coefficient and reference resistance

Background: A thermistor is a nonlinear sensor requiring a precise calibration technique to achieve accurate temperature measurements. This paper attempts to design a calibration technique employing artificial neural network (ANN) algorithms. The present work fulfills the following objectives: (i) to cover 100% input range in the linearity range measurement; (ii) to make the measurement technique adaptive to variations in reference resistance and thermistor temperature coefficient using a calibration technique. Methods: An ANN-based calibration circuit is cascaded to the data conversion circuit. Optimized ANN is trained with linear data independent of reference resistance and temperature coefficient effects on thermistor output. ANN optimization is performed by comparing various schemes, algorithms, and numbers of hidden layers to achieve a minimum mean square error and a regression close to 1. Results: The proposed technique provides a linear relationship for the system over the entire input range and avoids the requirement of repeated calibrations each time the thermistor is replaced. Practical data are used to validate the proposed measurement technique. Conclusions: The objectives and proposed technique have been demonstrated by results with a root mean square percentage error of 1.8%.

An Edge-Intelligent, Clip-on Rogowski Current Sensor With Wide Dynamic Range

Rogowski coil current sensors are popular solutions for current sensing having several advantages over current transformers (CTs), including size, bandwidth and dynamic range. These sensors have been used by electric utilities for gaining visibility into the electric grid directly helping in grid operations. This paper presents an overview of the design principles and test results for a PCB-based Rogowski coil that can be retrofitted around any existing conductor, resulting in a sensor that can be rapidly installed in the field. Due to the absence of any magnetic components in the coil, Rogowski coils cannot saturate and thus have a very high dynamic range, only limited by the accompanying signal conditioning or data converter circuits. In order to prevent saturation of the signal conditioning stage at higher current levels, a method to auto-tune the sensor has been presented, resulting in a dynamic range that is orders of magnitude higher than state of the art. The method, called dynamic range correction (DRC), uses edge intelligence to detect fault current scenarios and adjust the analog circuit to prevent saturation or distortion, while capturing the fault current waveforms. This feature enables post-event diagnostics for electric utilities at a very low cost.

A High-Throughput Energy–Area-Efficient Computing-in-Memory SRAM Using Unified Charge-Processing Network

This letter presents a computing-in-memory (CIM) static random-access memory (SRAM) using efficient data processing and conversion circuits to enhance the throughput, energy, and area efficiency performance. The proposed unified charge-processing network simultaneously provides both signal processing and data conversion functions with maximum resource utilization, realizing significant performance improvements in energy and area efficiency by 37.5% and 15.4%, respectively. Measurement results from a prototype fabricated in a 28-nm CMOS technology show that the proposed CIM SRAM achieves a high throughput of 186.18 GOPS, with energy and area efficiencies of 41.87 TOPS/W and 3288.4 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which demonstrates the performance improvements of 2.26×, 1.12×, and 2.89×, respectively, when compared with the state-of-the-art results. The proposed CIM SRAM can achieve 88.87% classification accuracy on the CIFAR-10 dataset.

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

Modeling Device Mismatch: Miles Copeland's Vision

The mid-1970s is widely regarded as the time when analog metal?oxide?semiconductor (MOS) circuits saw fundamental breakthroughs. Until then, almost all analog circuits were being built using bipolar transistors. Researchers at the University of California, Berkeley, showed the realization of data converter circuits using MOS capacitors [1], which was quickly followed by building pulse code modulation codecs that would eventually be incorporated into every telephone [2]. The next functional block that needed integration for voice telephony was filters for anti-aliasing and reconstruction purposes. In addition to Berkeley [3], a lesser-known center of excellence in Canada led the way. The Canadian team consisting of researchers from Carleton University (doctoral student C.F. Rahim) and Northern Telecom, both based in Ottawa, Canada, was headed by Prof. Miles A. Copeland [4]. They showed that precision analog filters could be realized by using a switched capacitor as a resistor equivalent. The accuracy of the filter is then decided by the matching of capacitors and not by the absolute value of any element. Thus the MOS capacitor became the precision element used in the data converters and filters. These inventions helped establish Northern Telecom as the leader in digital switching products for telephony.

Design of sampled analog wavelet processor architecture for cochlear implant application

This paper presents the design of sampled analog wavelet processor architecture for cochlear implant application using discrete Haar wavelet transform. Basic element of sampled analog wavelet processor architecture is operational amplifier based switched capacitor integrator circuit. This architecture distributes input signal frequencies into different predefined frequency band and based on cochlear sensitivity region for different frequencies by using arbitrary tree structure. The presented architecture is beneficial in terms of processing time of input signal, area and complexity by avoiding quantization and encoding process part of data converter circuits. Simulation results for this architecture is carried out with CMOS 90 nm technology.

A Practically Validated Intelligent Calibration Technique using Optimized ANN for Ultrasonic Flow meter

Design of an intelligent flow measurement technique by ultrasonic transducers using an Optimized Artificial Neural Network (OANN) is discussed in this paper. The objectives of the present work are (i) to extend the linearity range of flow measurement to 100% of full scale input range, (ii) to make the flow measurement technique adaptive to variations in (a) pipe diameter, (b) liquid density, (c) liquid temperature, and (iii) to achieve objectives (i) and (ii) by using an optimized artificial neural network. The output of an ultrasonic transducer is frequency. It is converted to voltage by using a suitable data conversion circuit. A suitable optimal ANN is added, in place of conventional calibration circuit, in cascade to data conversion circuit. ANN is trained, and tested with simulated data considering various values of pipe diameter, liquid density, and liquid temperature. The proposed technique is then subjected to practical data for validation. Results show that the proposed technique has fulfilled the desired objectives.

Research on Spectral Data Acquisition System

This paper introduces a kind of spectral data acquisition system based on the linear CCD. The spectral acquisition circuit, data conversion and storage circuit were designed. The synchronization of the spectral data acquisition, data conversion and storage were achieved using VHDL. Finally, the spectrum contained noise is processed by the wavelet denoising theory. The experimental results show that the proposed scheme is feasible.

Automatic Wiper System Based on the Adjacent Capacitive Edge Effect

An automatic wiper control system based on the adjacent capacitive used in automotive industry. Three types of capacitance sensor in different shapes (round-arrays, flower-shaped and single-ring) are designed, and their performances are simulated by using COMSOL and MATLAB under the same conditions. The results indicate the performance of the single-ring sensor is the best, and its sensitivity reaches 192.17fF/mm, which overcomes the problem of weak output. The data acquisition and conversion circuit based on digital chip AD7142 is designed to enhance the anti-interference and reduce the system cost. The experimental results prove the feasibility of the automatic wiper control system used on automatic car.

Advanced Ring-Shaped Microelectrode Assay Combined with Small Rectangular Electrode for Quasi-In vivo Measurement of Cell-to-Cell Conductance in Cardiomyocyte Network

To predict the risk of fatal arrhythmia induced by cardiotoxicity in the highly complex human heart system, we have developed a novel quasi-in vivo electrophysiological measurement assay, which combines a ring-shaped human cardiomyocyte network and a set of two electrodes that form a large single ring-shaped electrode for the direct measurement of irregular cell-to-cell conductance occurrence in a cardiomyocyte network, and a small rectangular microelectrode for forced pacing of cardiomyocyte beating and for acquiring the field potential waveforms of cardiomyocytes. The advantages of this assay are as follows. The electrophysiological signals of cardiomyocytes in the ring-shaped network are superimposed directly on a single loop-shaped electrode, in which the information of asynchronous behavior of cell-to-cell conductance are included, without requiring a set of huge numbers of microelectrode arrays, a set of fast data conversion circuits, or a complex analysis in a computer. Another advantage is that the small rectangular electrode can control the position and timing of forced beating in a ring-shaped human induced pluripotent stem cell (hiPS)-derived cardiomyocyte network and can also acquire the field potentials of cardiomyocytes. First, we constructed the human iPS-derived cardiomyocyte ring-shaped network on the set of two electrodes, and acquired the field potential signals of particular cardiomyocytes in the ring-shaped cardiomyocyte network during simultaneous acquisition of the superimposed signals of whole-cardiomyocyte networks representing cell-to-cell conduction. Using the small rectangular electrode, we have also evaluated the response of the cell network to electrical stimulation. The mean and SD of the minimum stimulation voltage required for pacing (VMin) at the small rectangular electrode was 166±74 mV, which is the same as the magnitude of amplitude for the pacing using the ring-shaped electrode (179±33 mV). The results showed that the addition of a small rectangular electrode into the ring-shaped electrode was effective for the simultaneous measurement of whole-cell-network signals and single-cell/small-cluster signals on a local site in the cell network, and for the pacing by electrical stimulation of cardiomyocyte networks.

Between the Textbook the the Lab Bench (review of "Analog circuit design: A Tutorial Guide to Applications and Solutions; Dobkin, B. and Williams, J.; 2011) [Book/Software Reviews

Analog Circuit Design covers the topics of power supplies, power management, data conversion, signal conditioning, and RF. The notes in the first half of the book go into great detail on switching power supply realization. Switching power supply realization is one of the great training grounds in engineering as it incorporates control theory, component limitations, layout effects, tricky measurements for speed and noise, and the need to design for a wide range of real-world specifications. Sections are also included on linear regulator design and powering optical components such as static sensitive lasers and thermoelectric coolers. Another excellent area for a broad education is building data conversion circuits. Application notes also include alot of information on data conversion history and verification.

A Smart Displacement Measuring Technique Using Linear Variable Displacement Transducer

This paper aims to design of a smart displacement measuring technique using Linear Variable Differential Transformer (LVDT). The objectives of this work are to (i) extend the linearity range of LVDT, (ii) eliminate the dependence of physical parameters of LVDT, (iii) eliminate the affect of input frequency and (iv) eliminate the effect of working temperature on the output of LVDT. The output of LVDT is differential ac voltages in secondary coils. It is converted to dc voltage by using a suitable data conversion circuit. An ANN block is added in cascade to data conversion unit. This arrangement helps to extend linearity range of the overall system and makes it independent of physical parameters of LVDT, input frequency and working temperature. Since the proposed smart displacement measuring technique produces output independent of physical parameters of LVDT, input frequency and working temperature, thus the present work avoids the requirement of repeated calibration every time the LVDT, input frequency or working temperature is varying.

A high-performance digital system for electrical capacitance tomography

This paper describes a recently developed digital-based data acquisition system for electrical capacitance tomography (ECT). The system consists of high-capacity field-programmable gate arrays (FPGA) and fast data conversion circuits together with a specific signal processing method. In this system, digital phase-sensitive demodulation is implemented. A specific data acquisition scheme is employed to deal with residual charges in each measurement, resulting in a high signal-to-noise ratio (SNR) at high excitation frequency. A high-speed USB interface is employed between the FPGA and a host PC. Software in Visual C++ has been developed to accomplish operational functions. Various tests were performed to evaluate the system, e.g. frame rate, SNR, noise level, linearity, and static and dynamic imaging. The SNR is 60.3 dB at 1542 frames s−1 for a 12-electrode sensor. The mean absolute error between the measured capacitance and the linear fit value is 1.6 fF. The standard deviation of the measurements is in the order of 0.1 fF. The dynamic imaging test demonstrates the advantages of high temporal resolution of the system. The experimental results indicate that the digital signal processing devices can be used to construct a high-performance ECT system.

LOW-POWER BIOMEDICAL SIGNAL MONITORING SYSTEM FOR IMPLANTABLE SENSOR APPLICATIONS

Implantable biomedical sensors and continuous real time in vivo monitoring of various physiological parameters requires low-power sensor electronics and wireless telemetry for transmission of sensor data. In this article, generic blocks required for such systems have been demonstrated with design examples. Ideally neural or electro-chemical sensor signal monitoring units comprise of low noise amplifiers, current or voltage mode analog to digital domain data conversion circuits and wireless telemetry circuits. The low-noise amplifier described here has a novel open loop amplifier scheme used for neural signal recording systems. The design has been implemented using 0.5-μm SOI-BiCMOS process. The fabricated chip can work with 1 V supply and consumes 805 nA. The current mode analog to digital conversion signal processing circuitry takes the current signal as an input and generates a pulse-width modulated data signal. The data signal is then modulated with a high frequency carrier signal to generate FSK data for wireless transmission. The design is fabricated in 0.5-μm standard CMOS process and consumes 1.1 mW of power with 3.5 V supply.

A CMOS-integrated microinstrument for trace detection of heavy metals

This paper presents a voltammetric microsystem which includes CMOS-integrated sensors, electronic interface, and data conversion circuits for enabling cost-effective, in situ detection of trace metals. The system's electronics were implemented in a 0.5 /spl mu/m, 5 V, CMOS process and occupy 36 mm/sup 2/. Single-chip integration of the system was accomplished using post-CMOS, thin-film fabrication techniques. Due to its reduced ambient noise coupling and an integrated, pseudo-differential potentiostat, this design provides the best figures of merit for detection limit, area, and power published to date for heavy-metal microinstruments. The microsystem dissipates 16 mW and has successfully detected lead at concentrations of 0.3 ppb on 3.2/spl times/10/sup -5/ cm/sup 2/ gold electrodes using subtractive anodic stripping voltammetry.

A simple built-in current sensor for IDDQ testing of CMOS data converters

This paper presents a simple built-in current sensor (BICS) design for quiescent current ( I DDQ) testing of CMOS data converter circuits. The proposed BICS works in two modes: the normal mode and the test mode. In the normal mode, the BICS is isolated from the circuit under test (CUT) due to which there is no performance degradation of the circuit. In the testing mode, the BICS detects the abnormal current caused by permanent manufacturing defects and has negligible impact on the performance of the circuit under test. The dynamic current of the CUT does not affect the BICS output. The BICS is operated from power supply voltages of the CUT using the current reference configuration. A 10-bit charge scaling digital-to-analog converter and a first-order modulator of an 8-bit sigma delta analog-to-digital converter have been designed in standard 1.5 μm CMOS and tested using the present BICS for injected faults simulating manufacturing defects. It is shown that significant improvement in testing of mixed signal integrated circuits has been achieved using a simple fault injection technique combined with the BICS.

Linearity improvement for the switched-capacitorDAC

Capacitor mismatch is the major source of nonlinearity for switched-capacitor data conversion circuits. A new approach to eliminate this effect is described. It is shown that this method provides almost inherent linearity.

Ultrasonic bloodstream diagnostic apparatus with dual displays of velocity profiles and average flow velocity

A ultrasonic bloodstream diagnostic apparatus wherein the frequencies of Doppler shift ultrasound information are analyzed by a frequency analyzer to derive a power spectrum represented by N-bit data. The N-bit data comprises (K+M+L) bits, where K represents the number of binary 0's in the highest order bit positions and varies in the range between zero and N-M, M represents a fixed number of significant bits immediately following the binary 0's and L represents the number of insignificant bits in the lowest order bit positions immediately following the M significant bits, where K+L equals N-M. A data compression technique is employed to conver the N-bit data to (m+l)-bit data by a data conversion circuit, with the m bits respectively identical to the M bits and l bits being a binary representation of the number of the L bits. A microprocessor derives a signal representing the average frequency of the power spectrum from the (m+l)-bit output data signal. The (m+l)-bit output data signal is converted by a conversion memory to a form suitable for display by an algorithm which reconverts it to N-bits and logarithmically compresses the latter.