Dielectric Damage Research Articles

Analysis of composite wavelength multilayer dielectric film damage based on the field-thermal effect

Taking SiO2/HfO2 multilayer dielectric films as the research object, when the total laser energy is the same, the effects of different laser parameters on film damage under 1064 nm and 355 nm composite wavelength pulse irradiation are analyzed. The results show that different energy ratios lead to exponential differences in the electron number density inside the film, but they are far from reaching the field damage threshold. Comprehensive analysis shows that film damage is mainly affected by thermal melt and stress. The greater the difference between an energy ratio of 1ω and 3ω, the greater the thermal stress in the film, the higher the stress peak, and the more obvious the damage effect of thermal stress on the film. Under the condition of 50%1ω, the thermal effect in the film is minimal, which can ensure that the film is not damaged as much as possible. The model method used in this paper only takes the current film system as an example for specific research and can be extended to all film systems for analysis.

Low-Temperature Deuterium Annealing for the Recovery of Ionizing Radiation-Induced Damage in MOSFETs

Ionizing radiation generates bulk traps (Not) as well as interface traps (Nit) in the gate dielectric. These traps cause unwanted threshold voltage (VTH) shifting, subthreshold swing (SS) and increased gate leakage current (IG). In this study, we used low-deuterium annealing (LTDA) as an alternative to conventional annealing, to minimize the side effects of thermal budget. Deuterium atom absorption was confirmed using secondary ion mass spectrometry (SIMS). DC characterizations are performed to analyze the recovery of the gate dielectric damages. Our results demonstrate that the proposed LTDA enables the curing of the gate dielectric damage caused by not only fabrication processing, but also by ionizing radiation. Operating deuterium annealing under low-temperature conditions can improve device performance, reliability, and device-to-device variability.

Characteristics and development of damage in the interface of polyimide multilayer films under a repetitive-frequency-pulsed voltage

To study the initiation and development of interfacial electrical damage in multi-layer dielectrics, an aging test of 3-layer polyimide films was conducted under pulsed voltage with a repetitive frequency of 500 Hz and a maximal amplitude of 30 kV. The variation in the damage morphology with the number of applied pulses was analyzed by a statistical method. The circuit current and partial discharge at different aging stages was measured, and the Fourier transform infrared spectrum analysis results of the aged and unaged sample regions were compared. The results demonstrate that the partial discharge in the dielectric interface gap, which is unavoidable in manufacturing, is the main cause of damage. It initiates from the interface and grows into the interior of the dielectric with the application of pulses. When there are no macroscopic defects on dielectric films, damage presents a punctiform morphology. The damage process can be divided into the following three stages: surface roughening damage, steady growth stage of damage points, and pre-breakdown stage. Differing from dielectrics without macroscopic defects, dielectrics with original void defects present transverse dendritic damage channels that initiate from the edge of the defect.

(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tried to demonstrate high-frequency back-end devices based on the gate-all-around stacked nanosheet low-temperature polycrystalline silicon channel (GAA NS LTPS). Fig.2 shows the current-voltage transfer characteristics of different width designs of LTPS and α-IGZO devices. The only way to enhance GAA NS LTPS RF devices with the same process is by increasing channels. However, it leads to a larger footprint, and the frequency doesn’t boost with increasing channels in proportion because of the capacitance between the multiple channels. In the meantime, the LTPS gate controllability becomes poor, and threshold voltage shifts significantly when the drive current is improved by widening channel width. Consequently, a-IGZO is adopted as the channel material of RF devices to solve the problem mentioned above. The a-IGZO film is back-end compatible and has transparency and high uniformity. The most important is that the gate controllability decay phenomenon is negligible no matter what the channel width is, which is helpful for different width designs. In contrast, IGZO devices can keep their threshold voltage and have ultra-low leakage current due to a large bandgap. According to the system on panel (SoP) trend, we attempt to integrate RFIC with the peripheral circuit on a substrate. Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined heterogeneous CFET (HCFET), which is demonstrated in the previous study [1]. In this talk, we will discuss HCFET architecture in detail. We compared junctionless mode (JL) and inversion mode (IM) for bottom p-type LTPS in HCFET. In our results, IM is better than JL as the junction structure for bottom PMOS because the requirement of the bottom channel in a HCFET is thin and width flexible for design. In addition, a trench gate of the bottom device plays an important role in HCFET. The trench tri-gate structure can avoid gate dielectric damage by plasma in the etching process, keep the top IGZO layer continuously and enhance performance compared to the general tri-gate structure. On the other hand, the gate of top n-type IGZO can be bottom gate only or dual gate for different requirements. Finally, HCFET can significantly reduce the distance between IGZO and p-type LTPS channels to save power and lower latency in the circuit.[1] S. -W. Chang et al., "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, April 2022, doi: 10.1109/TED.2021.3138947. Figure 1

Review of Radiation-Induced Effects on β-Ga2O3 Materials and Devices

β-Ga2O3 has become an ultimate choice of emerging new-generation material for its wide range of compelling applications in power electronics. In this review, we have explored the available radiations in the atmosphere and the effects of radiation on the β-Ga2O3 material and devices. The focus in this review summarizes various studies covering different radiation such as swift heavy ions, protons, neutrons, electrons, Gamma, and X-rays to understand the radiation-induced effects on the structure and their reliable performance in harsh environments. In addition, we focused on the various pre-existing defects in β-Ga2O3 and the emergence of radiation-induced defects that provoke a severe concern, especially from the device performance point of view. This review presents the irradiation-induced effects on the devices such as high-power devices such as Schottky barrier diodes (SBDs), field-effect transistors (FETs), metal-oxide-semiconductor (MOS) devices, and photodetectors. Some key studies including the changes in carrier concentration with a removal rate, Schottky barrier height (SBH), ideality factor, defect dynamics dielectric damage, interface charge trapping, a thermally activated recovery mechanism for charge carriers at elevated temperature, and diffusion length of minority charge carriers. These reports show that β-Ga2O3-based devices could be deployable for space or high-radiation terrestrial applications. These results provide/suggest a better device design based on the radiation degradation studies in the state-of-the-art β-Ga2O3 devices.

Lightning caused overvoltages on power transformers recorded by on-line transient overvoltage monitoring system

Transient overvoltages generated by lightning strikes or switching operations represent a significant risk to bushings and windings of power transformers. They cause stress on the insulation system and can, over time, cause dielectric failure and damage to power transformers. Many transformer failures are reported as dielectric failures and they are not necessarily linked to any particular event when they occur but may be the result of prior damage from transient overvoltage events. Lightning and switching overvoltage waveforms appearing at transformer terminals in real operating conditions may significantly differ from standard impulse voltage waveforms used during laboratory testing. The number and amplitudes of overvoltages which stress the insulation depend on various parameters such as the lightning strike density in the considered area, since it determines how often the transformer is stressed by lightning overvoltages. Since the overvoltage amplitudes at transformer terminals are usually unknown, an on-line overvoltage transient recorder can be used with the ability to sample, analyse and store transients in real-time. In this paper, an on-line transient overvoltage monitoring system (TOMS) for power transformers is presented that is capable to continuously record in real-time various kinds of transient overvoltages such as lightning or switching overvoltages. Special attention is paid to lightning caused transient overvoltages recorded at the terminals of 150 MVA power transformer. Recorded waveforms originating from lightning strikes to overhead lines are correlated with data from the lightning location system (LLS) and supervisory control and data acquisition (SCADA) system. Collected data about overvoltage stresses can be used as the basis for the assessment of the transformer insulation condition, estimation of health index and for analysis of various kinds of events such as faults or equipment failures.

Electrochemical assessment of dielectric damage to phospholipid bilayers by amyloid β-Oligomers

Amyloid beta (Aβ1-42) oligomers produced in vitro with and without the oligomerization inhibitor hexafluoroisopropanol (HFIP) were studied and compared as agents inflicting damage to the phospholipid bilayers. Tethered lipid membranes (tBLMs) of different compositions were used as model membranes. Dielectric damage of tBLMs by Aβ1-42 oligomers was monitored by the electrochemical impedance spectroscopy (EIS). Membranes containing sphingomyelin exhibited the highest susceptibility to Aβ1-42 oligomers when assembled in the absence of an inhibitor. The activation barrier of ion translocation through the Aβ1-42 oligomer entities in tBLMs was lowest in sphingomyelin membranes (<15 kJ/mol). This is consistent with the formation of water-filled, highly conductive (>50 pS) nanopores in tBLMs by Aβ1-42 oligomers assembled without HFIP. Conversely, HFIP-generated Aβ1- 42 oligomers exhibited conductance with high activation energies (>38 kJ/mol), suggesting the formation of assemblies with relatively narrow ion pores and the effective conductance in the range < 15 pS. Finally, the EIS data analysis revealed differences in the lateral distribution of Aβ1-42 oligomers in tBLMs. The inhibitor-free Aβ1-42 oligomers populate the tBLM surface in a random manner, whereas the HFIP-generated Aβ1-42 oligomers tend to cluster forming surface areas with markedly different densities of Aβ1-42 defects.

Using N-Norms for Analyzing Symmetric Protective Electrical Circuits with Triple Modal Reservation

The redundancy of functional blocks and critical assemblies in radio-electronic equipment is among the most widely used techniques for increasing reliability. Complex redundant systems raise the problem of electromagnetic compatibility (EMC). Ignoring EMC requirements can lead to partial or complete REE failures. In this paper, the authors analyze a noise-protective electrical circuit with triple modal reservation (a promising type of cold redundancy). A multilayer stripline is investigated, the conductors of which are symmetrically arranged relative to two planes. On account of the strong electromagnetic coupling, this protective circuit can decompose dangerous ultra-wideband (UWB) interference received at the input of the primary or redundant circuits into unipolar pulses of lower amplitude. Using this approach, due to the symmetry of the conductors, equal decomposition efficiency could be achieved. However, the effect of UWB interference at the input of one of the conductors produces bipolar pulses at the output of the other conductors. In this paper, the authors evaluate the dangers of unipolar and bipolar decomposed pulses and use modal analysis to mathematically determine the polarities and amplitudes of the decomposed pulses at all output nodes for a pseudo-matched structure. By using the quasistatic approach with and without losses, the time responses to a trapezoidal pulse with a total duration of 60 ps, which simulates UWB interference, are obtained. To confirm the results of modal analysis and quasistatic simulation, an experimental study is performed. Using a stroboscopic oscilloscope DSA 8300, the authors obtained a transient response to a step excitation. Then, taking the derivative, the response to a trapezoidal pulse with a total duration of 140 ps was obtained. To analyze the criticality of the decomposed pulses, N-norms are used. In the general case, it is shown that the UWB interference is decomposed into four pulses of lower amplitude. At the same time, the value of each N-norm indicates its significant attenuation. For example, the amplitude of the UWB pulse acting on the input of the reserved conductor decreases by 10.31–8.93 times. Such results numerically demonstrate the high efficiency of the suggested approach when it comes to protecting equipment against UWB interference. It is also shown that the probability of dielectric breakdown and damage to electronic components in redundant circuits is lower than in a primary circuit. This is due to the fact that the value of N3 in the redundant circuit is 2.38 times less than in the primary circuit. However, the results demonstrate that arcing is highly probable both in primary and redundant circuits. Finally, aspects of symmetry/asymmetry in the problem under investigation are emphasized.

Search for copper diffusion at hybrid bonding interface through chemical and electrical characterizations

Cu/SiO2 diffusion at hybrid bonding interface without diffusion barrier was investigated in order to validate the electrical insulation of interconnects. The Cu thermal diffusion was studied by ToF-SIMS analysis of the dielectrics stack facing bonding pads after a bonding annealing (400 °C, 2 h) and a diffusion annealing (400 °C, 14 h). No trace of copper was found above the limit of detection 1017 at·cm−3. Cu ions drift was followed by I-V measurements on specially designed comb-serpentine that maximize the electrical field at bonding interface. Their efficiency was confirmed since physical failure analysis located the dielectric breakdown damage between bonding pads. Breakdown voltages coupled to wafer-to-wafer misalignments enabled the extraction of the SiO2 breakdown strength: 3.4 MV·cm−1. This study proves that at room temperature, hybrid bonding interconnects remain electrically insulated despite thermal budgets involved by the bonding process.

Lateral profiling of gate dielectric damage by off-state stress and positive-bias temperature instability

Gate dielectric degradation caused by off-state stress (OSS) and positive-bias temperature instability (PBTI) was analyzed in terms of charge trapping inside the gate dielectric and at the interface. Under the same degree of stress voltage, the OSS damage caused more degradation of threshold voltage (VT) than the PBTI damage. When the two stresses were alternately applied to an n-channel MOSFET, they effectively produced a leftward shift in the VT. This was because a greater negative VT shift was produced by the OSS and a less positive VT shift was produced by the PBTI. By analyzing the characteristics of the gate induced drain leakage (GIDL), it was determined that charge trapping inside the gate dielectric was more localized on the drain side than on the source side after OSS, but was distributed at a relatively similar level along the channel length direction after PBTI. To analyze the interface traps caused by OSS and PBTI, charge pumping (CP) measurements were conducted to map their lateral distribution along the channel direction. The PBTI-induced interface traps were found to be symmetrically distributed on the source side and drain side, while the OSS-induced interface traps were more concentrated toward the drain side.

Temperature Effect on Performance of Enhancement Mode Al0.4Ga0.6n-Channel Moshfets with Hybrid Oxide

The metal oxide semiconductor heterostructure field effect transistors (MOSHFETs) based on AlxGa1-xN materials with the high aluminum composition is a promising choice for high-power, high-temperature harsh environment applications. In the present work the temperature stability of MOSHFETS with high-k ZrO2, Al2O3 gate dielectrics has been studied. Our data show these high-k dielectrics introduce negative fixed charges (Qox) as high as 1-3×1013 cm-2 depleting 2DEG density of 2×1013 cm-2 causing a positive shift of threshold voltage (VTH) compared to that for HFET which is an important feature for realizing enhanced (E-) mode MOSHFET. ZrO2 possesses higher Qox resulting in stronger positive VTH shift in devices, while devices with Al2O3 demonstrate lower gate leakage. To take advantages of both oxides, UWBG Al0.4Ga0.6N channel E-mode MOSHFET has been fabricated. E-mode device was realized using the hybrid oxide (ZrO2/Al2O3) combined with gate recess. To separate effects of dielectric charges and damage from recess process on device performance depletion (D-) mode and E-mode devices were fabricated on the same wafer simultaneously. D-mode devices were protected during gate recess step to avoid additional damage. Thermally induced VTH instability of these MOSHFETs were studied and potential mechanism for this VTH instability is discussed. Experimental: Figure 1(a) shows the pseudomorphic device structure that was grown using metalorganic chemical vapor deposition on AlN/sapphire templates. A graded composition (AlxGa1-xN, x=1-0.4) back barrier reduces internal stress and improves gate control in the devices.[i] , [ii] The top 200 Å thick graded n-AlxGa1-xN (x from 0.6 to 0.3) layer assists with the formation of ohmic contacts resistance as low as 1.7 Ω-mm. The n-doping of this layer compensates the positive charges resulting from the reverse composition grading.[iii] The 2DEG sheet resistance was ~1900 ohm/□. Device processing details published elsewhere.[iv] The fixed gate-length LG ≈ 2.0 μm, source to drain spacing, LSD=6 μm, were used for regular devices with 15 μm channel width, while for precise C(V,T,f) measurements we use a test structure with gate area 200x80 μm2 . Results and discussion: The combination of gate recessing and hybrid oxide resulted in threshold-voltage (VTH) shift of +12.2 V from D to E-mode device (Figure 1(b)). The gate leakage current in both D and E-mode MOSHFETs is ~103 smaller than that of MOSHFETs using singe Al2O3 or ZrO2 layer (Figure 2(a)) which allows us to apply gate voltage as high as +12 V. The peak DC currents for D and E-mode devices were found to be 1.1 A/mm and 0.48 A/mm respectively while in the pulse mode it was 1.3 A/mm and 0.53 A/mm. ON/OFF ratio as high as 3×108 was achieved which is higher than ~2 orders of magnitude than that for Al2O3 or ZrO2. We then performed temperature dependent threshold and gate leakage study of our fabricated MOSHFETs. Figure 2(b) shows the temperature dependent gate leakage characteristics of MOSHFETs of this study. It has been found that, in the D-mode MOSHFET, the VTH experiences positive VTH shift of + 1.7 V from RT to 150 °C; for the E-mode MOSHFET the shift is negative: -2.9 V (Figure 3(a)). The VTH shift for similar device having Schottky gate (no dielectric) (HFET) is significantly smaller, +0.2 V. This shows that the VTH shift is mainly due to the charges in dielectric or at dielectric-barrier interface. In the E-mode devices, the effective channel mobility and VTH was additionally affected by radiative defects introduced during gate-recess step. The mobility (µ) in D-mode devices decreases with temperature while it increases for the E-mode devices. We estimated temperature dependent interface state density (DIT(T)) and Qox (T) using frequency- dependent C-V measurements as shown in Figure 3(b). Our analysis show that in D-mode device, Qox(T) dominates over interface charges. These are fixed negative charges which deplete the channel giving a total VTH shift of +1.7 V from RT to 150°C. The extracted SS value for D and E-mode devices were 99 mV/decade and 134 mV/decade, indicating an increased density of interface traps (DIT) at the recessed interface in the E-mode device. Larger DIT value in E-mode devices caused by a radiation damage from the barrier recessing process and becomes comparable with Qox. Thus the temperature effect on Qox is compensated by DIT changes, increasing SS and making the VTH(T) more negative.[i]) G. Simin et al., Jpn. J. Appl. Phys., 40, L1142 (2001).[ii]) C. Ren et al., J. Semicond. 36, 014008-1 (2015).[iii]) S. Bajaj et al., Appl. Phys. Lett. 109, 133508-1 (2016).[iv]) S. Mollah et al., Appl. Phys. Lett. 117, 232105 (2020). Figure 1

Linear‐Nonlinear Optical and Quantum Chemical Studies on Quinolinium 4‐Aminobenzoate: A Third Order Non‐Linear Optical Material for Optoelectronic Applications

AbstractGood quality single crystals of a non‐linear optical (NLO) material, quinolinium 4‐aminobenzoate (ABAQ), are grown by employing solution growth technique. The crystal structure is confirmed via single crystal X‐ray diffraction studies. Grown crystals of the ABAQ compound are characterized by powder X‐ray diffraction, Fourier transform infrared, thermal analysis, and mechanical studies. Ultraviolet–vis–near infrared (UV–vis–NIR) and photoluminescence spectra reflect the optical transmission range of the obtained compound. Dielectric studies and laser damage threshold measurement are carried out to verify the non‐linear activity and surface resistance of the grown crystal. From the Kurtz Perry powder technique, the second harmonic generation efficiency of the ABAQ compound is estimated to be 90% that of the standard potassium dihydrogen phosphate. Z‐Scan technique is performed to investigate the non‐linear behavior of ABAQ crystal. The suitability of ABAQ material for optical limiting and switching applications is also verified. Computational analysis performed upon the stable geometry of ABAQ molecule using density functional theory strongly supports the experimental findings with a significant chemical background. The non‐linear behavior of the title compound is determined by investigating various non‐linear optical (NLO) parameters of electric dipole moment, polarizability, and hyperpolarizability. Based on these inferences, the ABAQ material can be declared as a promising material for optical limiting and switching applications in optoelectronics regime.

Investigation of Fluoro-Carbon Layer on Dense Sicoh Formed during CF4 and CF4/C4F6 Based Continuous Wave Plasma Etch

Motivation: Plasma etching of low-k and ultra low-k (ULK) dielectric materials have seen a tremendous growth in deep nanoscale applications. Fluorocarbon based gases are the forerunners in etching low-k dielectrics as they are the F suppliers necessary to remove Si and C from SiCOH material. Different FC gases in combination with the additive gases contribute differently to the etch behavior of SiCOH due to differing reaction chemistry and formation of Fluorocarbon layer as an interfacial layer between plasma front and dielectric front [i]. Due to dynamic formation and etching of FC Layer happening at the dielectric surface, understanding FC layer properties in each gas plasma is the starting step to control etch rate and plasma induced damage in Low-k dielectrics. This paper aims to study and compare FC layer deposition by different gases grouped into CF4 and CF4/C4F6 family with N2, O2 and H2 as additive gases in each group. FC layer thickness, etch rate, optical properties of etched SiCOH and chemical composition of the FC layer by different plasma treatments have been presented in this work. Methodology: Dense SiCOH (k=2.75 and Open Porosity: 7%) with initial thickness of 157±3nm is deposited on 300mm Si Wafer with a thin SiO2 adhesion layer in between. These wafers are blanket etched in a commercial etch chamber with the given gas combinations (CF4, CF4/N2, CF4/O2, CF4/H2; CF4/C4F6, CF4/C4F6/N2, CF4/C4F6/O2, CF4/C4F6/H2) for same amount of time, total gas flow rate, similar power, pressure and temperature settings.Post Etch blanket wafers are subjected to various in-line and off-line metrology tools. In-line spectroscopic ellipsometer is used to model complex refractive index and thickness of individual layers. Tauc-Lorentz model best describes the FC layer whereas Cauchy model describes the dielectric [ii]. In-line XPS was carried out to probe the surface of FC layer and gain chemical information. Furthermore depth profile of etched layer is carried out by sputtering the surface with low power Ar ions to study variations in chemical composition with the layer depth. SEM is used to see the cross section profile and verify the results from above method Observation: Thickness evaluation from the dispersion models shows that the CF4 group has higher etch rate and lower FC layer thickness compared to CF4/C4F6 group. C4F6 has higher polymerization ability by the virtue of its lower F/C ratio. Amongst each group, Oxygen as additive gas shows the highest etch rate and least FC thickness followed by Nitrogen whereas Hydrogen has least etch rate but highest FC layer thickness. Under given etch conditions with CF4/C4F6/H2 plasma, deposition rate was higher than etching rate leading to stack growth (Fig.1a). Hydrogen supports polymerization by scavenging Fluorine away and aids in thicker FC films.XPS chemical composition shows Fluorine diffusion through FC layer into the dielectric layer bringing changes to its pristine structure. This affects Carbon% across the etched dielectric thickness (Fig.1b). Thicker the FC layer is, closer is the Carbon % to pristine SiCOH. Presence of surficial Nitrogen in the nitrogen containing plasmas shows nitrogen reacts with SiCOH Carbon, forms CN compounds and increases the etch rate. FC layer shows presence of CF3 radicals on the surface and decrease fast with the depth, followed by CF2 radicals. CF radicals are in larger quantity and are present deepest into the FC Layer. Presence of polymerized C-C and C-CFx bonds increases with the FC Layer depth and offset with increase of C-Si bond near the SiCOH interface. Conclusion: This paper shows comparison of Etch Rate and FC layer thickness during SiCOH etch using different gas combinations in the CCP plasma chamber. Thickness correlation between ellipsometric model data and XPS depth profile followed by SEM cross section measurement of layer thickness point towards the correctness of dispersion models for each layer. These models can be used for quick inline post etch metrology useful for process control. O2 containing plasmas are too aggressive on the dielectric with negligible FC layer formation, while H2 containing plasmas are less damaging but exhibit very small etch rate. CF4/C4F6/N2 plasma is the optimum combination for Low-k dielectric etch amongst other combinations in terms of desired etch rate and lower reduction in Carbon %. Relative concentration and penetration depth of different CFx radicals in FC film suggests its influence on film structure.

SmartHeating: On the Performance and Lifetime Improvement of Self-Healing SSDs

In NAND flash memory-based solid-state drives (SSDs), during the idle time between the consecutive program/erase cycles (dwell time), the dielectric damage of flash cell can be partially repaired, also known as the self-recovery effect. As the effectiveness of the self-recovery effect can be improved under high temperature, self-healing SSDs are proven feasible to extend the flash endurance significantly. However, current self-healing SSDs perform the heating operations on all the worn-out blocks without considering the data retention requirement, and measures the lifetime of flash memory based on the worst-case self-recovery effect, leading to some unnecessary heating operations and the degraded performance. We propose SmartHeating, a smart heating scheme that exploits the dwell time variation and the write hotness variation to improve the I/O performance and the lifetime of self-healing SSDs. SmartHeating tracks the dwell time of all worn-out flash blocks, predicts their self-recovery effect and reliability, and avoids performing heating operations on the worn-out flash blocks that still have strong flash reliability. In addition, by exploiting the data hotness variation, SmartHeating only heats the worn-out flash blocks that store write-cold data, while allocating write-hot data to a small portion of worn-out flash blocks with negligible refresh overhead. The experimental results show that SmartHeating reduces the number of heating operations by 12.5% on average, boosts I/O performance of flash storage systems by 21.0%, and improves the lifetime of flash memory by $1.20\times $ compared with conventional heating scheme.

Curing of Aged Gate Dielectric by the Self-Heating Effect in MOSFETs

Gate dielectric damage caused by both internal and external stresses is becoming worse because of aggressive complementary metal-oxide-semiconductor (CMOS) scaling. However, conventional technologies for damage reduction using thermal annealing during fabrication have some limitations. As a result, there is a growing demand for technologies that will cure CMOS damage as a new paradigm for improving long-term reliability. This review paper reexamines self-recovery technologies, which are fully compatible with CMOS fabrication. Although self-heating has long been considered an unwanted operating side effect, it can also be favorably utilized to cure damage. Generated Joule heat arising from device operation can uniformly anneal the gate dielectric and effectively recover damage in various devices, such as conventional logic, memory, and aerospace CMOS devices, as well as thin-film transistors for displays.

Modeling the dielectric breakdown strength and energy storage density of graphite-polymer composites with dielectric damage process

Recent experimental data has demonstrated significant influences of graphite volume concentration on the dielectric breakdown and energy storage behavior of graphite-polymer composites, but no existing homogenization theory has been established to illustrate such dependence in the context of alternating current (AC) loading. In this paper we develop a novel homogenization scheme to connect the microstructural parameters of constituent phases and the AC frequency to the dielectric breakdown strength and energy storage density of the overall composite. The major microstructural features covered are the graphite volume concentration, imperfect bonding effect, graphite aspect ratio, percolation threshold, filler-dependent electron tunneling, Maxwell-Wagner-Sillars polarization, and frequency-dependent electron hopping and dielectric relaxation. A thermodynamic framework is developed to describe the evolution of a dielectric damage parameter with respect to the electric field. We highlight the developed theory with validation through the experimental data of graphite/PVDF composite over a wide range of graphite volume concentration and AC frequency. The results indicate that the dielectric breakdown strength of the graphite-polymer composite decreases with respect to the graphite volume concentration, while the energy storage density increases with it.

Optimal Design and Testing of the Driving Coil on Induction Coilgun

The driving coil, as a key element of synchronous induction coilgun, endures not only the radial expansionary force because of the magnetic flux compression but also the axial force due to the compressive force and counterforce of the armature. Dielectric breakdown and mechanical structure damage occurs frequently. Meanwhile, the driving coil should have high energy conversion efficiency as a pusher to accelerate the armature. Therefore, it is important to choose the appropriate structure and parameters in order to achieve a high launching performance. In this paper, the factors that influence the system efficiency are analyzed first. Different structure designs of the driving coil with the same inductance are evaluated. The effect of different calibers on the system efficiency is analyzed. The simulation result shows that the structure of the driving coil should be chosen according to the practical launching requirement while the magnetic coupling should be increased. Second, the electromagnetic force applied on the coil is calculated and the stress is analyzed. The thickness and displacement of the containment are calculated on the condition of unyielding. In order to validate the accuracy of the theoretical analysis, an electromagnetic-mechanical coupling finite element model is built. Comparing two calculation results, the error is small. Therefore, the method can be used to guide the design of the driving coil. Finally, a driving coil is fabricated according to the calculation results and experimented through static and dynamic tests. The experimental results show that the driving coil performs well and have high conversion efficiency. It provides a theoretical and experimental basis for the future design of multistage induction coilgun.

Power reduction for recovery of a FinFET by electrothermal annealing

A strategy of reducing the power consumption to cure gate dielectric damage by electrothermal annealing (ETA) is proposed. A tri-gate FinFET was fabricated to demonstrate the damage curing by the ETA. Localized Joule heat induced by high current flowing through dual gate electrodes successfully annealed the damaged gate dielectric. Furthermore, a design methodology to save power consumption during the ETA was explored. Electrical measurements and simulations were performed considering scaling-down and material engineering points of view. This work contributes to improving the reliability of the FinFET by developing the ETA approach with reduced power consumption.

Experimental Evaluation of Switching Induced Transformer Resonance Mitigation

Vacuum circuit breaker switching induced transients can cause frequency induced medium voltage transformer dielectric damage, where the two are coupled with short cable. The most common mitigation method is to add a resistor/capacitor snubber at the transformer terminals. While this approach has proved highly effective, there is little discussion of variations on the snubber application. This paper describes the results of switching tests of a vacuum circuit breaker connected to a 1-MVA transformer through medium voltage cable. First, the mechanism was investigated. The tests show the resonance is induced by the broadband frequency content due to the high dv/dt of the circuit breaker current chopping and the chopping rate. Next, snubber performance at various circuit locations was tested. The snubber was most effective at the transformer medium-voltage terminals and at the load side of the circuit breaker.

Growth study and characterization of KDP crystals grown by 2D translation method

Transparent potassium dihydrogen phosphate (KDP) crystals that are grown from different translational velocities and orientation configurations were obtained during growth through a novel motion mode called 2D translation method. The grown crystals were investigated by microhardness, dielectric, chemical etching, thermal analysis and laser damage threshold studies. A higher mechanical hardness is observed in crystals grown by the 2D translation method than that grown by the rotating-crystal method. Low dielectric loss and less dislocation density show that the 2D translation method grown crystals contain minimum defects. The thermal stability and damage threshold of the 2D translation method grown crystals are higher than those of the crystal grown using the rotating-crystal method. Moreover, the properties of various crystals grown by the 2D translation method under different conditions are compared, and results show that the grown crystals' quality is best when the translation velocity is 0.04 m/s.