This study investigates the characteristics, sensitive regions, and failure mechanism of 'soft errors' caused by Spacecraft charging induced Electrostatic Discharge (SESD) in a full custom 130 nm Fully Depleted Silicon-On-Insulator (FD-SOI) D flip-flop (DFF) device through SPICE simulation and SESD experiment at room temperature. The results showed that the main characteristic of the soft errors caused by the SESD was manifested in bit '1' upset in the DFF cells, and the SESD sensitive regions were located at the reset and power pins. The possible failure mechanism in the DFF circuit was the misrecognition of the reset signal and the recoverable breakdown of its inner P-channel Metal Oxide Semiconductor (PMOS) circuit induced by the SESD transients.