Cylindrical Surrounding Gate Research Articles

Small Signal Parameters Extraction and RF Performance of GaN-Based Dual-Metal Cylindrical Surrounding Gate Junctionless Accumulation-Mode (DM-CSG-JAM) MOSFET

In this paper, small-signal model parameters and RF characteristics of the GaN-based Dual-Metal Cylindrical Surrounding Gate-Junctionless Accumulation Mode (DM-CSG-JAM) MOSFET has been extracted. Better scattering parameters has been observed for GaN-based DM-CSG-JAM MOSFET over other analogous structures which confirms its applications for RF domain. Also, enhanced drain current, transconductance, cut-off frequency, I on/I off ratio, etc. have been observed for the GaN-based device. The performance of the GaN-based MOSFET has also been compared with the other compound semiconductors (GaAs, InP) and silicon-based DM-CSG-JAM MOSFET. On account of the eminent properties possessed by GaN, the GaN-based device shows outstanding characteristics over the other semiconductor-based device.

Analytical model for junctionless accumulation‐mode cylindrical surrounding gate (JAM‐CSG) MOSFET as a biosensor

AbstractThis article proposes analytical modeling for Junctionless Accumulation‐Mode Cylindrical Surrounding Gate (JAM‐ CSG) MOSFET‐based biosensor used for label free electrical detection of the biomolecules (enzymes, cells, DNA, etc.). Modeling has been performed using the Poisson's equation and considering parabolic potential profile. A nanogap cavity is being created for providing a binding site for the biomolecules. Influence of both the neutral and charged biomolecules immobilized in the nanogap cavity has been studied. The change in the threshold voltage is being utilized as a measure for detecting the existence of the biomolecules inside the cavity region. The sensitivity parameter has also been found considering different cavity heights. ATLAS device simulator has been utilized for conducting the simulations. Furthermore, the analytical model outcomes are validated with the simulated ones. Results acquired verify the considered device to be able to work as a highly sensitive biosensor.

Analysis of Subthreshold Swing of Junctionless Cylindrical Surrounding Gate MOSFET Using Stacked High-k Gate Oxide

Analysis of Subthreshold Swing of Junctionless Cylindrical Surrounding Gate MOSFET Using Stacked High-k Gate Oxide

Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-<i>k</i> oxide

<abstract> <p>We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO<sub>2</sub>/high-<italic>k</italic> dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-<italic>k</italic> dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-<italic>k</italic> dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-<italic>k</italic> dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-<italic>k</italic> dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO<sub>2</sub>/ZrO<sub>2</sub>, La<sub>2</sub>O<sub>3</sub>, and TiO<sub>2</sub> with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL.</p> </abstract>

Assessment of Quantum Scaling Length Model for Cylindrical Surrounding Double-Gate (CSDG) MOSFET

Aim: The aim of this study is the derivation and assessment of quantum scaling length of Cylindrical Surrounding Double-Gate (CSDG) MOSFET with respect to Silicon body thickness. Objectives: To derive the quantum natural length of CSDG MOSFET with respect of Silicon body Thickness, observe the behaviour of the CSDG MOSFET at the nanoscale regime and compare the behaviour of the CSDG MOSFET with Cylindrical Surrounding Gate (CSG) MOSFET. Methods: The authors employed the mathematical analysis. The quantum energy level is analysed using Schrodinger equation by assuming one-dimensional approach and a negligible potential well. Results: The analytical results obtained from classical and quantum natural length are compared with the numerical simulations. Also, the model was compared with CSG MOSFET. Results show that proposed analytical close-form expression that approximately matches the numerical simulation, and the proposed CSDG MOSFET will be better than CSG MOSFET at quantum level even though it has smaller quantum natural length than CSG MOSFET. Conclusion: In this research work, quantum scaling length model and quantum scaling factor have been proposed using the quantum confinement approach. The performance assessment of the CSDG MOSFETs provided an opportunity of determining the scaling limit of CSDG MOSFETs by evaluating the trade-off between the quantum natural length and the classical natural length of CSDG MOSFETs. Results obtained were compared with CSG MOSFETs to show that CSDG MOSFETs offer better device characteristics.

Temperature dependency and linearity assessment of dual-metal gate stack junctionless accumulation-mode cylindrical surrounding gate (DMGS-JAM-CSG) MOSFET

A physics-based temperature-dependent analytical model for a Dual- Metal Gate Stack Junctionless Accumulation-Mode Cylindrical Surrounding Gate (DMGS-JAM-CSG) MOSFET has been presented in this paper by solving the 2D Poisson’s equation utilizing the suitable boundary conditions. The device performance is examined at various temperatures (T = 100K, 300K and 500K) by observing several parameters like potential, electric field, electron concentration and electron velocity. The obtained outcomes are also contrasted with the outcomes acquired after simulation. Further, the device is also analyzed for its analog performance. Lastly, to check the relevancy of the device for RFIC applications, linearity assessment is performed by evaluating its several figure of merits (FOMs) like second-order and third-order Voltage Intercept Points (VIP2, VIP3), third-order Intercept Input Power (IIP3), third-order Intermodulation Distortion (IMD3) and various higher order transconductances. The obtained results are contrasted with an analogous device and it is discovered that DMGS- JAM- CSG MOSFET device acquires better electrical and linearity characteristics. ATLAS 3D device simulator has been utilized to conduct the simulations.

Analytical Drain-Current Model and Surface-Potential Calculation for Junctionless Cylindrical Surrounding-Gate MOSFETs

In this paper, we propose an analytical drain-current model for long-channel junctionless (JL) cylindrical surrounding-gate MOSFET (SRG MOSFET). It is based on surface-potential solutions obtained from Poisson’s equation using some approximations and separate conditions. Furthermore, analytical compact expressions of the drain-current have been derived for deep depletion, partial depletion, and accumulation mode. The confrontation of the model with TCAD simulation results, performed with Silvaco Software, proves the validity and the accuracy of the developed model

Analytical Drain-Current Model and Surface-Potential Calculation for Junctionless Cylindrical Surrounding-Gate MOSFETs

In this paper, we propose an analytical drain-current model for long-channel junctionless (JL) cylindrical surrounding-gate MOSFET (SRG MOSFET). It is based on surface-potential solutions obtained from Poisson’s equation using some approximations and separate conditions. Furthermore, analytical compact expressions of the drain-current have been derived for deep depletion, partial depletion, and accumulation mode. The confrontation of the model with TCAD simulation results, performed with Silvaco Software, proves the validity and the accuracy of the developed model

A 2D Unified Subthreshold Drain Current Investigation for Junctionless Cylindrical Surrounding Gate(JCSG) Silicon Nanowire Transistor

A 2D Unified Subthreshold Drain Current Investigation for Junctionless Cylindrical Surrounding Gate(JCSG) Silicon Nanowire Transistor

A Quasi 2-D Electrostatic Potential and Threshold Voltage Model for Junctionless Triple Material Cylindrical Surrounding Gate Si Nanowire Transistor

A mathematical model used for determining the threshold voltage characteristics and electrostatic potential of a Junctionless Triple Material Cylindrical Surrounding Gate Silicon Nanowire Transistor (JLTMCSGSiNWT) is proposed in this research work and is obtained by resolving the poison equation. Three materials with dissimilar metal functions are used in the construction of the device gate structure. Device parameters used to determine the electrical characteristics are also included in the model. Behavior of the device is investigated through its vertical electrical field distribution along the device channel. Higher drain bias conditions leading to DIBL are reduced in the proposed structure by minimal variation of voltages owing to three different gate materials that maintain a steady field distribution along the channel. This model explicitly shows the impact of various criteria like drain bias voltage, gate bias voltage, thickness of the silicon layer, thickness of the oxide layer, and length of the channel on electrostatic potential and the deterioration of threshold voltage. The proposed analytical model is validated with TCAD simulations and it could be further extended to study the advanced electrical characteristics of the JL Triple Material CSG Silicon Nanowire Transistor.

A physical model of cylindrical surrounding double-gate metal-oxide-semiconductor field-effect transistor

<sec>The cylindrical surrounding double-gate metal-oxide-semiconductor field-effect transistor (CSDG MOSFET) is formed by adding an internal control gate to the cylindrical surrounding-gate (CSG) MOSFET. The inner gate of CSDG MOSFET acts as a second gate for enhanced charge control. At present, the research of CSDG MOSFET structure is widely concerned. Compared with double-gate MOSFET, triple-gate MOSFET and CSG MOSFET, the CSDG MOSFET provides good controllability of the gate over the channel. Additionally, the device allows for higher volume inversion than CSG MOSFET, which leads to better output characteristics.</sec><sec>In order to study the electrical characteristics of CSDG MOSFET, the potential model of CSDG MOSFET is obtained by solving the two-dimensional Poisson equation in cylindrical coordinates. The effects of gate dielectric, channel length and gate dielectric thickness on the surface potential and electric field of CSDG MOSFET are studied. Besides, the drain-source current model of CSDG MOSFET is established by integrating the inverse charge along the channel. The effects of gate dielectric and gate dielectric thickness on the transconductance of CSDG MOSFET are studied. In addition, the effects of the downscaling of device parameters on the transfer characteristics and transconductance of CSDG MOSFET are studied.</sec><sec>The electrical characteristics of CSDG MOSFET are analyzed and discussed. The results show that the minimum surface potential along the channel of CSDG MOSFET decreases with the increase of gate dielectric constant of gate dielectric layer. The electric field along the channel and along the radius, drain-source current and transconductance of CSDG MOSFET increase as the gate dielectric constant increases. The threshold voltage of CSDG MOSFET decreases as the gate dielectric constant increases. Moreover, with the downscaling of device parameters, the transfer characteristics and transconductance of CSDG MOSFET decrease. The performance of CSDG MOSFET can be significantly improved by using high-k gate dielectrics. </sec>

Sensitivity of Lightly and Heavily Dopped Cylindrical Surrounding Double-Gate (CSDG) MOSFET to Process Variation

This research work analyzes the sensitivity of Cylindrical Surrounding Double-Gate (CSDG) MOSFET to process variation using the Poisson equation’s analytical solution. This work has been verified with the numerical simulation. Also, the results obtained have been compared with a multi-gate device known as Cylindrical Surrounding Gate (CSG) MOSFETs. The lightly and heavily doped CSDG MOSFETs have been realized. Their immunity to parameter variation (channel length, Silicon thickness, and Random Dopant Fluctuations (RDFs)) has been compared to CSG MOSFET. This research work indicates that lightly doped CSDG MOSFET exhibits the slightest threshold variations than CSG MOSFETs. It confirms that the lightly doped CSDG MOSFET has better immunity to channel variation than CSG MOSFETs. This is due to its structure and inherent internal and external gate geometry, which offers greater control over the channel. However, RDFs become a dominating factor for heavily doped CSG and CSDG MOSFETs, leading to more dispersion in the threshold variations. Therefore, the CSDG MOSFET’s immunity to channel variation becomes deteriorated due to the larger surface-to-volume ratio. At this point, the CSG MOSFET tends to offer better immunity to process variation. Hence, the sensitivity of threshold voltage to parameter variations depends entirely on the RDFs, as the heavily doped devices are aggressively scaled to the nanometer regime.

Surface Potential modeling of Dual Metal Gate-Graded Channel-Dual Oxide Thickness with two dielectric constant different of Surrounding Gate MOSFET

An Analytical study for the surface potential, threshold voltage and Subthreshold swing (SS) of Dual-metal Gate Graded channel and Dual Oxide Thickness with two dielectric constant different cylindrical gate surrounding-gate (DMG-GC-DOTTDCD) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed to investigate short-channel effects (SCEs). The performance of the modified structure was studied by developing physics-based analytical models for the surface potential, threshold voltage shift, and Subthreshold swing. It is shown that the novel MOSFET could significantly reduce threshold voltage shift and Subthreshold swing, can also provides improved electron transport and reduced short channel effects (SCE). Results reveal that the DMG-GC-DOTTDCD devices with different dielectric constant offer superior characteristics as compared to DMG-GC-DOT devices. The derived analytical models agree well with simulation by ATLAS.

A compact model for gate tunneling currents in undoped cylindrical surrounding-gate metal-oxide-semiconductor field-effect transistors

We present a compact model of the gate tunneling current in cylindrical surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs) based on quantum mechanical correction. The model is physics-based and is given in an analytical closed form. We start by deriving a quadratic approximation of the quantum electrostatic potential with the two lowest energy levels using quantum perturbation theory. In addition, small-diameter cylindrical SG MOSFETs can be described excellently by taking both structural and electrical confinement effects into account. A self-consistent Schrödinger-Poisson simulation was used as a benchmark to assess the proposed model. It was found that the calculated gate tunneling currents determined using the model matched well with the corresponding currents derived using self-consistent calculations. The model is thus useful for fast analysis of gate tunneling currents within the context of a circuit simulator.

Study of Interface Trapped Charges Effect on Performance of Junction Less Trial Material Cylindrical Surrounding-Gate MOSFETs

Study of Interface Trapped Charges Effect on Performance of Junction Less Trial Material Cylindrical Surrounding-Gate MOSFETs

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

An analytical model for terahertz detection in cylindrical surrounding-gate MOSFETs

An analytical model for detection of terahertz radiation by plasma wave in cylindrical surrounding-gate (SRG) MOSFETs is presented. In comparison with traditional drain-current models, the rectification response of terahertz signal due to current self-mixing in conducting channel is considered by solving coupled plasma fluid equations using perturbation method. The resulted model is for the first time dipicting detector response in above threshold, near threshold and subthreshold regimes by a single expression valid for both resonant and nonresonant detection schemes. As no fitting parameters is adopted, the model is physical and predicative. Model validity has been extensively verified through numerically solving differential equations with a wide range of incident wave frequencies, channel doping concentrations, device working temperatures, SRG MOSFET geometry parameters as well as incident wave amplitudes. Model applicability to large input terahertz signal has also been discussed. The presented model is convenient for finding the optimum detector design from a multiparameter space. Its great universality will make it a candidate compact model for future terahertz integrated circuit simulation.

SPICE Model of Drain Induced Barrier Lowering in Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET

SPICE Model of Drain Induced Barrier Lowering in Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET

Multidimensional Nano Heat Conduction in Cylindrical Transistors

A 3-D non-Fourier heat conduction in a cylindrical surrounding-gate (SG) MOSFET including phonon-wall collisions effects has been developed and presented. The obtained results are verified with the existent data. The various thermal characteristics of the device are obtained from the solution of the dual-phase-lag model coupled with a 3-D second-order temperature jump boundary condition. We find that, when the Fourier law ceases to be valid, the presented model is able to predict the nano heat transfer in cylindrical devices. After switching off the device, we show that the temperature is more thermally stable then that given in MOSFET and tri-gate silicon on insulator-MOSFET. We show also that the radius of the cylindrical SG drastically changes the temperature and heat flux distributions within the transistor devices.

Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement

A charge plasma technique based dopingless (DL) accumulation mode (AM) junctionless (JL) cylindrical surrounding gate (CSG) MOSFET has been proposed and extensively investigated. Proposed device has no physical junction at source to channel and channel to drain interface. The complete silicon pillar has been considered as undoped. The high free electron density or induced N+ region is designed by keeping the work function of source/drain metal contacts lower than the work function of undoped silicon. Thus, its fabrication complexity is drastically reduced by curbing the requirement of high temperature doping techniques. The electrical/analog characteristics for the proposed device has been extensively investigated using the numerical simulation and are compared with conventional junctionless cylindrical surrounding gate (JL-CSG) MOSFET with identical dimensions. For the numerical simulation purpose ATLAS-3D device simulator is used. The results show that the proposed device is more short channel immune to conventional JL-CSG MOSFET and suitable for faster switching applications due to higher I ON/I OFF ratio.