Cylindrical Surrounding Gate MOSFET Research Articles

Analysis of subthreshold swing in junctionless cylindrical surrounding gate MOSFET using gaussian doping profile

Analysis of subthreshold swing in junctionless cylindrical surrounding gate MOSFET using gaussian doping profile

Analysis of Subthreshold Swing of Junctionless Cylindrical Surrounding Gate MOSFET Using Stacked High-k Gate Oxide

Analysis of Subthreshold Swing of Junctionless Cylindrical Surrounding Gate MOSFET Using Stacked High-k Gate Oxide

Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-<i>k</i> oxide

<abstract> <p>We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO<sub>2</sub>/high-<italic>k</italic> dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-<italic>k</italic> dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-<italic>k</italic> dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-<italic>k</italic> dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-<italic>k</italic> dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO<sub>2</sub>/ZrO<sub>2</sub>, La<sub>2</sub>O<sub>3</sub>, and TiO<sub>2</sub> with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL.</p> </abstract>

Assessment of Quantum Scaling Length Model for Cylindrical Surrounding Double-Gate (CSDG) MOSFET

Aim: The aim of this study is the derivation and assessment of quantum scaling length of Cylindrical Surrounding Double-Gate (CSDG) MOSFET with respect to Silicon body thickness. Objectives: To derive the quantum natural length of CSDG MOSFET with respect of Silicon body Thickness, observe the behaviour of the CSDG MOSFET at the nanoscale regime and compare the behaviour of the CSDG MOSFET with Cylindrical Surrounding Gate (CSG) MOSFET. Methods: The authors employed the mathematical analysis. The quantum energy level is analysed using Schrodinger equation by assuming one-dimensional approach and a negligible potential well. Results: The analytical results obtained from classical and quantum natural length are compared with the numerical simulations. Also, the model was compared with CSG MOSFET. Results show that proposed analytical close-form expression that approximately matches the numerical simulation, and the proposed CSDG MOSFET will be better than CSG MOSFET at quantum level even though it has smaller quantum natural length than CSG MOSFET. Conclusion: In this research work, quantum scaling length model and quantum scaling factor have been proposed using the quantum confinement approach. The performance assessment of the CSDG MOSFETs provided an opportunity of determining the scaling limit of CSDG MOSFETs by evaluating the trade-off between the quantum natural length and the classical natural length of CSDG MOSFETs. Results obtained were compared with CSG MOSFETs to show that CSDG MOSFETs offer better device characteristics.

Temperature dependency and linearity assessment of dual-metal gate stack junctionless accumulation-mode cylindrical surrounding gate (DMGS-JAM-CSG) MOSFET

A physics-based temperature-dependent analytical model for a Dual- Metal Gate Stack Junctionless Accumulation-Mode Cylindrical Surrounding Gate (DMGS-JAM-CSG) MOSFET has been presented in this paper by solving the 2D Poisson’s equation utilizing the suitable boundary conditions. The device performance is examined at various temperatures (T = 100K, 300K and 500K) by observing several parameters like potential, electric field, electron concentration and electron velocity. The obtained outcomes are also contrasted with the outcomes acquired after simulation. Further, the device is also analyzed for its analog performance. Lastly, to check the relevancy of the device for RFIC applications, linearity assessment is performed by evaluating its several figure of merits (FOMs) like second-order and third-order Voltage Intercept Points (VIP2, VIP3), third-order Intercept Input Power (IIP3), third-order Intermodulation Distortion (IMD3) and various higher order transconductances. The obtained results are contrasted with an analogous device and it is discovered that DMGS- JAM- CSG MOSFET device acquires better electrical and linearity characteristics. ATLAS 3D device simulator has been utilized to conduct the simulations.

Analytical Drain-Current Model and Surface-Potential Calculation for Junctionless Cylindrical Surrounding-Gate MOSFETs

In this paper, we propose an analytical drain-current model for long-channel junctionless (JL) cylindrical surrounding-gate MOSFET (SRG MOSFET). It is based on surface-potential solutions obtained from Poisson’s equation using some approximations and separate conditions. Furthermore, analytical compact expressions of the drain-current have been derived for deep depletion, partial depletion, and accumulation mode. The confrontation of the model with TCAD simulation results, performed with Silvaco Software, proves the validity and the accuracy of the developed model

Analytical Drain-Current Model and Surface-Potential Calculation for Junctionless Cylindrical Surrounding-Gate MOSFETs

In this paper, we propose an analytical drain-current model for long-channel junctionless (JL) cylindrical surrounding-gate MOSFET (SRG MOSFET). It is based on surface-potential solutions obtained from Poisson’s equation using some approximations and separate conditions. Furthermore, analytical compact expressions of the drain-current have been derived for deep depletion, partial depletion, and accumulation mode. The confrontation of the model with TCAD simulation results, performed with Silvaco Software, proves the validity and the accuracy of the developed model

Sensitivity of Lightly and Heavily Dopped Cylindrical Surrounding Double-Gate (CSDG) MOSFET to Process Variation

This research work analyzes the sensitivity of Cylindrical Surrounding Double-Gate (CSDG) MOSFET to process variation using the Poisson equation’s analytical solution. This work has been verified with the numerical simulation. Also, the results obtained have been compared with a multi-gate device known as Cylindrical Surrounding Gate (CSG) MOSFETs. The lightly and heavily doped CSDG MOSFETs have been realized. Their immunity to parameter variation (channel length, Silicon thickness, and Random Dopant Fluctuations (RDFs)) has been compared to CSG MOSFET. This research work indicates that lightly doped CSDG MOSFET exhibits the slightest threshold variations than CSG MOSFETs. It confirms that the lightly doped CSDG MOSFET has better immunity to channel variation than CSG MOSFETs. This is due to its structure and inherent internal and external gate geometry, which offers greater control over the channel. However, RDFs become a dominating factor for heavily doped CSG and CSDG MOSFETs, leading to more dispersion in the threshold variations. Therefore, the CSDG MOSFET’s immunity to channel variation becomes deteriorated due to the larger surface-to-volume ratio. At this point, the CSG MOSFET tends to offer better immunity to process variation. Hence, the sensitivity of threshold voltage to parameter variations depends entirely on the RDFs, as the heavily doped devices are aggressively scaled to the nanometer regime.

A physical model of cylindrical surrounding double-gate metal-oxide-semiconductor field-effect transistor

<sec>The cylindrical surrounding double-gate metal-oxide-semiconductor field-effect transistor (CSDG MOSFET) is formed by adding an internal control gate to the cylindrical surrounding-gate (CSG) MOSFET. The inner gate of CSDG MOSFET acts as a second gate for enhanced charge control. At present, the research of CSDG MOSFET structure is widely concerned. Compared with double-gate MOSFET, triple-gate MOSFET and CSG MOSFET, the CSDG MOSFET provides good controllability of the gate over the channel. Additionally, the device allows for higher volume inversion than CSG MOSFET, which leads to better output characteristics.</sec><sec>In order to study the electrical characteristics of CSDG MOSFET, the potential model of CSDG MOSFET is obtained by solving the two-dimensional Poisson equation in cylindrical coordinates. The effects of gate dielectric, channel length and gate dielectric thickness on the surface potential and electric field of CSDG MOSFET are studied. Besides, the drain-source current model of CSDG MOSFET is established by integrating the inverse charge along the channel. The effects of gate dielectric and gate dielectric thickness on the transconductance of CSDG MOSFET are studied. In addition, the effects of the downscaling of device parameters on the transfer characteristics and transconductance of CSDG MOSFET are studied.</sec><sec>The electrical characteristics of CSDG MOSFET are analyzed and discussed. The results show that the minimum surface potential along the channel of CSDG MOSFET decreases with the increase of gate dielectric constant of gate dielectric layer. The electric field along the channel and along the radius, drain-source current and transconductance of CSDG MOSFET increase as the gate dielectric constant increases. The threshold voltage of CSDG MOSFET decreases as the gate dielectric constant increases. Moreover, with the downscaling of device parameters, the transfer characteristics and transconductance of CSDG MOSFET decrease. The performance of CSDG MOSFET can be significantly improved by using high-k gate dielectrics. </sec>

Channel Length Scaling Pattern for Cylindrical Surrounding Double-Gate (CSDG) MOSFET

The natural length of MOSFETs helps to describe the potential distribution in the Silicon substrate. This natural length varies in different device structures, from a single gate to multi-gate device geometry. To measure the short channel effects degree, the natural length should be known because various vital parameters such as OFF-current, Roll-off threshold voltage, and drain induced barrier lowering depend on it. In this research work, authors have presented a scaling theory for Cylindrical Surrounding Double-Gate (CSDG) MOSFET, which guide the device design. The scaling method has been derived, based on the application of the Poisson equation, in a cylindrical structure using Parabolic Potential Approximation (PPA) along the radial direction (substrate part only). Furthermore, a comparison with cylindrical surrounding-gate MOSFETs, Silicon-on-insulator, and double-gate device geometries has been obtained. The results obtained using the PPA model show that CSDG MOSFET has the least natural length, making it a better component for SCEs immunity.

Study of Interface Trapped Charges Effect on Performance of Junction Less Trial Material Cylindrical Surrounding-Gate MOSFETs

Study of Interface Trapped Charges Effect on Performance of Junction Less Trial Material Cylindrical Surrounding-Gate MOSFETs

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

An analytical model for terahertz detection in cylindrical surrounding-gate MOSFETs

An analytical model for detection of terahertz radiation by plasma wave in cylindrical surrounding-gate (SRG) MOSFETs is presented. In comparison with traditional drain-current models, the rectification response of terahertz signal due to current self-mixing in conducting channel is considered by solving coupled plasma fluid equations using perturbation method. The resulted model is for the first time dipicting detector response in above threshold, near threshold and subthreshold regimes by a single expression valid for both resonant and nonresonant detection schemes. As no fitting parameters is adopted, the model is physical and predicative. Model validity has been extensively verified through numerically solving differential equations with a wide range of incident wave frequencies, channel doping concentrations, device working temperatures, SRG MOSFET geometry parameters as well as incident wave amplitudes. Model applicability to large input terahertz signal has also been discussed. The presented model is convenient for finding the optimum detector design from a multiparameter space. Its great universality will make it a candidate compact model for future terahertz integrated circuit simulation.

An insight into the high frequency analysis of work function modulated cylindrical surrounding gate MOSFET

The unique design along with greater accuracy in device performance has made cylindrical surrounding gate MOSFET (CSGM) a cutting edge device in the present VLSI technology. Due to its cylindrical geometry, this device provides higher packing density and higher scaling possibilities. In this work, a work function engineering based metal gate with continuous mole fraction variation along the z-axis in a cylindrical surrounding gate MOSFET (WMCSGM) is introduced. The proposed WMCSGM model exhibits improved RF performance as compared to conventional CSGM model. The static gm-VGS curve and Cgg-VGS curves are investigated clearly. The relevant electrical parameters such as threshold voltage (Vth), drain current (Id) and transconductance are extracted. Along with the electrical parameters, RF parameters and gain parameters (current gain and voltage gain) and different performance measures (cut-off frequency, maximum oscillation frequency) have been extensively investigated.

An insight into the high frequency analysis of work function modulated cylindrical surrounding gate MOSFET

The unique design along with greater accuracy in device performance has made cylindrical surrounding gate MOSFET (CSGM) a cutting edge device in the present VLSI technology. Due to its cylindrical geometry, this device provides higher packing density and higher scaling possibilities. In this work, a work function engineering based metal gate with continuous mole fraction variation along the z-axis in a cylindrical surrounding gate MOSFET (WMCSGM) is introduced. The proposed WMCSGM model exhibits improved RF performance as compared to conventional CSGM model. The static gm-VGS curve and Cgg-VGS curves are investigated clearly. The relevant electrical parameters such as threshold voltage (Vth), drain current (Id) and transconductance are extracted. Along with the electrical parameters, RF parameters and gain parameters (current gain and voltage gain) and different performance measures (cut-off frequency, maximum oscillation frequency) have been extensively investigated.

SPICE Model of Drain Induced Barrier Lowering in Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET

SPICE Model of Drain Induced Barrier Lowering in Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET

Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement

A charge plasma technique based dopingless (DL) accumulation mode (AM) junctionless (JL) cylindrical surrounding gate (CSG) MOSFET has been proposed and extensively investigated. Proposed device has no physical junction at source to channel and channel to drain interface. The complete silicon pillar has been considered as undoped. The high free electron density or induced N+ region is designed by keeping the work function of source/drain metal contacts lower than the work function of undoped silicon. Thus, its fabrication complexity is drastically reduced by curbing the requirement of high temperature doping techniques. The electrical/analog characteristics for the proposed device has been extensively investigated using the numerical simulation and are compared with conventional junctionless cylindrical surrounding gate (JL-CSG) MOSFET with identical dimensions. For the numerical simulation purpose ATLAS-3D device simulator is used. The results show that the proposed device is more short channel immune to conventional JL-CSG MOSFET and suitable for faster switching applications due to higher I ON/I OFF ratio.

Assessment of analog RF performance for insulated shallow extension (ISE) cylindrical surrounding gate (CSG) MOSFET incorporating gate stack

In this paper, insulated shallow extension cylindrical surrounding gate (ISE-CSG) MOSFET with high-k gate stack has been proposed and extensively investigated. The performance of high-k ISE-CSG MOSFET has been compared with cylindrical surrounding gate MOSFET. ISE-CSG with high-k gate stack has number of desirable features at 30 nm regimes. The results reveal that ISE-CSG MOSFET with gate stack is more immune to short channel effects because of improved carrier transportation capability. It has been observed that high-k ISE-CSG MOSFET shows improved figure of merits as drive current (ION), ION/IOFF ratio, transconductance (gm), cutoff frequency fT, transconductance generation factor, intrinsic gain (Av), transconductance frequency product, gain transconductance frequency product and gain frequency product. ISE-CSG with high-k gives better control over the depletion region and therefore it is a suitable device for high speed, high frequency and analog/RF circuit applications.

Performance analysis of undoped and Gaussian doped cylindrical surrounding-gate MOSFET with it's small signal modeling

The scaling of the solid-state devices are reaching its limit and it enhances the significant short channel effects. To overcome these problems, the surrounding-gate MOSFET is emerging as a promising structure and is a replacement of traditional MOSFETs. In this research work, authors have analyzed the performance of various parameters for the cylindrical surrounding-gate MOSFET using surface potential based approach and further transformation of variable technique to find the solution of the same differential equation. However, the modeling of terminal charge and trans-capacitance are also presented which is used for the circuit simulation. The influence of Gaussian doping (in vertical direction across the radius of the device) has been analyzed and solution of the surface-potential is derived based on the taylor series expansion.

The Influence of High-k Material/SiO<sub>2</sub> Gate Stacks on Direct Gate Tunneling Current of Cylindrical Surrounding-Gate MOSFETs

In this paper, we present a model of gate tunneling current in cylindrical surrounding-gate MOSFETs through dual layer high-k dielectric/SiO2 stacks. The model was derived under a quantum perturbation theory by taking into account both structural and electrical confinement effects. The influences of high-k materials and SiO2 thickness on the gate tunneling current have been studied. The calculated results show that the HfO2 is the most effective high-k material to decrease the gate tunneling current. It is also shown that the gate tunneling current is reduced with the SiO2 thickness. In addition, the obtained tunneling currents are fitted well with those obtained under the self-consistent calculation.