Cyclic ADC Research Articles

3,300万画素120fps CMOSイメージセンサ用カラム並列2段サイクリック型A/D変換回路の低消費電力設計

A 12-bit, two-stage cyclic analog-to-digital converter (ADC) for a 33-megapixel 120-fps CMOS image sensor with low power consumption was developed by analyzing the relationship between the processed bit number and power consumption in the first- and second-stage ADCs, respectively. The power consumption of a two-stage cyclic ADC per column driven at 120 fps was reduced to 101 µW after 12 bits were separated into the upper 4 bits of the conversion in the first-stage ADC and the lower 8 bits of the conversion in the second-stage one. It exhibits a maximum differential non-linearity of -0.7/+0.5 LSB and a random noise of 148.5 µVrms, both of which are sufficient for the sensor. Owing to the low power consumption ADC, the sensor showed a low power consumption of 2.32 W in conjunction with a high frame rate of 120 fps and a high resolution of 33 Mpixels. The quality of the images taken by the image sensor is good enough for use in full-spec Super Hi-Vision.

A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters

A 33-megapixel 120-frames/s (fps) CMOS image sensor has been developed. The 7808 × 4336 pixel 2.8-μm pixel pitch CMOS image sensor with 12-bit, column-parallel, two-stage, cyclic analog-to-digital converters (ADCs) and 96 parallel low-voltage differential signaling output ports operates at a data rate of 51.2 Gb/s. The pipelined operation of the two cyclic ADCs reduces the conversion time. This ADC architecture also effectively lowers the power consumption by exploiting the amplifier function of the cyclic ADC. The CMOS image sensor implemented with 0.18-μm technology exhibits a sensitivity of 0.76 V/lx·s without a microlens and a random noise of 5.1 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> with no column amplifier gain and 3.0 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> with a gain of 7.5 at 120 fps while dissipating only 2.45 and 2.67 W, respectively.

CALORIC: A Readout Chip for High Granularity Calorimeter

A very-front-end electronics has been developed to fulfil requirements for the next generation of electromagnetic calorimeters. The compactness of this kind of detector and its large number of channels (up to several millions) impose a drastic limitation of the power consumption and a high level of integration. The electronic channel proposed is first of all composed of a low-noise Charge Sensitive Amplifier (CSA) able to amplify the charge delivered by a silicon diode up to 10pC. Next, a two-gain shaping, based on a Gated Integration (G.I.), is implemented to cover the 15 bits dynamic range required: a high gain shaper processes signals from 4 fC (charge corresponding to the MIP) up to 1pC, and a low gain filter handles charges up to 10 pC. The G.I. performs also the analog memorization of the signal until it is digitalized. Hence, the analog-to-digital conversion is carried out through a low-power 12-bit cyclic ADC. If the signal overloads the high-gain channel dynamic range, a comparator selects the low-gain channel instead. Moreover, an auto-trigger channel has been implemented in order to select and store a valid event over the noise. The timing sequence of the channel is managed by a digital IP. It controls the G.I. switches, generates all needed clocks, drives the ADC and delivers the final result over 12 bits. The whole readout channel is power controlled, which permits to reduce the consumption according to the duty cycle of the beam collider. Simulations have been performed with Spectre simulator on the prototype chip designed with the 0.35μm CMOS technology from Austriamicrosystems. Results show a non-linearity better than 0.1% for the high-gain channel, and a non-linearity limited to 1% for the low-gain channel. The Equivalent Noise Charge referred to the input of the channel is evaluated to 0.4 fC complying with the MIP/10 limit. With the timing sequence of the International Linear Collider, which presents a duty cycle of 1%, the power consumption of the complete channel is limited to 43 μW thanks to the power pulsing. The total area of the channel is 1.2 mm2 with an analog memory depth of 16.

A 1.25 ps Resolution 8b Cyclic TDC in 0.13 $\mu$m CMOS

This paper describes the first implementation of the well-known cyclic ADC architecture into a time-to-digital converter. With an asynchronous clocking scheme, an all-digital 1.5b time-domain multiplying DAC (MDAC) is repetitively used for 8b conversion. The MDAC is based on a 2 × time amplifier with an offset-compensated gain calibration scheme. The proposed cyclic TDC, fabricated in a 0.13 μm CMOS, shows a resolution of 1.25 ps with a total conversion range of ±160 ps, the maximum operating frequency of 100 MHz, and a power consumption of 4.3 mW at 50 MHz. The measured DNL and INL are ± 0.7 LSB and - 3 to + 1 LSB, respectively.

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC

A low temporal noise and high dynamic range CMOS image sensor is developed. A 1Mpixel CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> (1.2e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> ) temporal noise, 82 dB dynamic range using 64 samplings in the folding-integration ADC mode. Very high variable gray-scale resolution of 13b through 19b is attained by changing the number of samplings of pixel outputs. The implemented CMOS image sensor using a 0.18-μm technology has the sensitivity of 10- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> /lx·s, the conversion gain of 67- μV/e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> , and linear digital code range of more than 4 decades.

Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs

This paper presents a design-for-diagnosis method to identify error sources in pipelined analog-to-digital converters (ADCs). In the proposed method, the stage under test (SUT) is configured to separate each error effect contained in its output residual signal. Two stages after the SUT are configured as a cyclic ADC to digitize the residual output voltage of the SUT. Critical circuit parameters, namely, op-amp gain, capacitor mismatch, op-amp offset, and comparator offset, are identified in the digital domain. Accurate analog test input signals are not necessary for the proposed design-for-diagnosis scheme. A simple digital decoder is employed to generate test control signals. Several additional switches are used to perform SUT re-configuration, which induce minor area overhead. Behavioral and circuit simulations are performed to show the effectiveness of the proposed method.

A 240-frames/s 2.1-Mpixel CMOS Image Sensor With Column-Shared Cyclic ADCs

This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu{\hbox{m}}$</tex></formula> 1P4M process with pixel pitch of 2.25 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox{m}}$</tex> </formula> . The designed 10-bit ADC dissipates only 90 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu\hbox{W/channel}$</tex></formula> with 1.5 V supply. The measured DNL and INL are <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$+$</tex> </formula> 0.59/ <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 0.83 LSB and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$+$</tex> </formula> 2.8/ <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.

Signal Processing for High Granularity Calorimeter: Amplification, Filtering, Memorization, and Digitalization

A dedicated very-front-end (VFE) readout channel for high-granularity calorimeters has been designed, fabricated and evaluated. This electronics is composed of a low-noise charge-sensitive amplifier followed by a bandpass filter based on a gated integrator. The efficiency of the gated integrator, a time-variant filter, in terms of noise rejection has been compared to an equivalent time-invariant filter, a CRRC shaper. Their serial and parallel noise indexes have been evaluated by simulation for different values of integration and peaking times. Results show that the gated integrator is a more efficient filter than the CRRC shaper, thanks to the time of integration which can be expanded to approach the time interval between two successive bunch crossings, whereas the peaking time of the CRRC shaper is limited by pile-up considerations. Moreover, the gated integrator intrinsically includes the capacitor required to perform the analog memorization of the signal before its delayed digital conversion. This analog-to-digital conversion is carried out by a 12-bit cyclic ADC specifically developed for this application. The very-front-end channel has been evaluated using a 0.35 μm CMOS technology. Measurements show a global non-linearity better than 0.1%. The Equivalent Noise Charge at the input of the channel is evaluated to 1.8 fC, to be compared to the maximum input charge of 10 pC. The power consumption of the complete channel is limited to 6.5 mW.

A 14 b 23 MS/s 48 mW Resetting $\Sigma \Delta$ ADC

High-resolution, moderate-speed, calibration-free analog-to-digital converters (ADCs) are becoming increasingly difficult to design in low-voltage nanometer-scale CMOS processes. We propose an ADC architecture based on a resetting ΣΔ modulator that achieves high resolution, despite poor component matching and poor analog transistor performance. A prototype design pipelines a second-order resetting ΣΔ modulator and a 10 b cyclic ADC. The device achieves 14 b resolution and samples as a Nyquist converter at 23 MS/s. This calibration-free ADC achieves no missing codes, 87 dB SFDR and 11.7 b ENOB. The ADC is fabricated in 0.18 μm CMOS and occupies a core area of 0.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It consumes 48 mW from a 2 V supply.

Leading-Subcycles Capacitor Error-Averaging Scheme for Cyclic ADCs

This paper proposes a leading-subcycles capacitor error-averaging (LCEA) scheme to reduce the capacitor mismatch error of cyclic analog-to-digital converters (ADCs) while only slightly lowering the conversion rate. The scheme does not need complicated structures or extra calibration circuits. Hence, the proposed LCEA scheme can be used for cyclic ADCs to achieve high accuracy while maintaining their low-power and small-area features. In addition, the figure of merit (FOM) versus the number of averaging operations in a complete conversion cycle is analyzed such that power-accuracy-speed tradeoffs can be optimized. A proof of concept 12-bit cyclic ADC is implemented to compare the performance of the proposed LCEA scheme with that of a conventional cyclic ADC. The chip is fabricated in a 3.3-V, 0.35-μm CMOS process. Measurements demonstrate that the cyclic ADC with only two averaging operations has a 6 dB and 10 dB higher signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), respectively, than the conventional cyclic ADC, and with only a slightly reduced conversion rate of 12/13 times than that of the conventional cyclic ADC. In addition, the measured FOM is greatly reduced to 0.55 times of that obtained using the conventional scheme which indicates the advantage of the LCEA technique.

A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction

A low power 10-bit 250-k sample per second (KSPS) cyclic analog to digital converter (ADC) is presented. The ADC's offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence. The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator's offset errors and switched capacitor mismatch errors. With this structure, it has the advantages of simple circuit configuration, small chip area and low power dissipation. The cyclic ADC manufactured with the Chartered 0.35 μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate. It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42 × 0.68 mm2.

Signal processing for high granularity calorimeter: amplification, filtering, memorization and digitalization

A very-front-end electronics dedicated to high granularity calorimeters has been designed and its performance measured. This electronics performs the amplification of the charge delivered by the detector thanks to a low-noise Charge Sensitive Amplifier. The dynamic range is improved using a bandpass filter based on a Gated Integrator. Studying its weighting function, we show that this filter is more efficient than standard CRRC shaper, thanks to the integration time which can be expand near the bunch interval time, whereas the peaking time of the CRRC shaper is limited to pile-up consideration. Moreover, the Gated Integrator performs intrinsically the analog memorization of the signal before its delayed digital conversion. The analog-to-digital conversion is performed through a 12-bit cyclic ADC specifically developed for this application.The very-front-end channel has been fabricated using a 0.35 μm CMOS technology. Measurements show a global non-linearity better than 0.1%. The Equivalent Noise Charge at the input of the channel is evaluated to 1.8 fC, compare to the maximum input charge of 10 pC. The power consumption of the complete channel is limited to 6.5 mW.

A Double-Gain, Large Dynamic Range Front-end ASIC With A/D Conversion for Silicon Detectors Read-Out

We present a prototype of an application specific integrated circuit (ASIC) featuring an input dynamic range of more than 52 pC. The ASIC is designed to read out signals from large-capacitance silicon detectors used in Si-W calorimeters for high-energy astroparticle physics experiments. The ASIC features a double-gain Charge Sensitive Amplifier (CSA), which uses a real-time automatic gain selection circuitry to switch between the input ranges of [0-2.4 pC] and [0-52.6 pC]. A Correlated Double Sampling (CDS) filter follows the CSA and completes the front-end chain. A complete analog channel dissipates 2.8 mW. The present prototype also includes 9 cyclic ADC channels, in view of the final objective of this project, which will be a 16-channel chip with digitized outputs.

A Distortion-Compensated Charge Transfer Amplifier for a 1.66-MHz Cyclic Pipeline ADC

A distortion-compensated charge transfer amplifier (DCCTA) is proposed to improve the linearity constraints of the differential charge transfer amplifier (DCTA). The proposed DCCTA effectively reduces distortion at its output by source degeneration, cross coupling, and making the drain-to-source voltage of the amplifying transistor independent of the applied input signal. This DCCTA yields an effective number of bits of 9.26 bits, compared with 6.05 bits for the DCTA at 40 MHz while consuming only 13.5 μW from a 1.2-V source. A 1.66-MHz cyclic pipeline analog-to-digital converter employing this DCCTA as a residue amplifier was simulated using 90-nm CMOS process, resulting in a peak resolution of 9.21 bits, without being limited by the thermal noise.

DCD – The Multi-Channel Current-Mode ADC Chip for the Readout of DEPFET Pixel Detectors

The current-mode ADC chip-prototype for the readout of DEPFET particle pixel-detectors with high spatial resolution is presented. The planned application of these DEPFET detectors are vertex detectors for ILC and Belle II. The chip has 72 ADC channels. Every channel processes the input signals using two cyclic ADCs that operate in parallel. The cyclic ADCs are based on current-mode memory cells. The measured signal to noise ratio of one ADC is about 660 (fast ADC variant: 520) and its conversion time is 320 ns (fast ADC variant: 160 ns) in the case of 8-bit resolution. Redundant signed-digit cyclic conversion is used for automated digital error correction. One ADC-core occupies only 40 ?m × 55 ?m, its static power consumption is 0.96 mW. Besides the two ADCs, every channel contains a regulated cascode and two additional current-mode memory cells that allow double-sampling of the input signal. Due to the need for high radiation tolerance, the chip has been implemented in a 180 nm CMOS technology using enclosed NMOS gate layouts. Novel radiation-hard circuits have been used. The chip has also been used to read out a small DEPFET test matrix.

A 0.02-mm$^{2}$ 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology

A 9-bit cyclic ADC employs a track-and-evaluation technique for enhancing the speed of residue evaluation. The proposed multiply-by-two circuit has a shorter evaluation time than the conventional design due to the application of a partial positive feedback topology. The residue evaluation and sampling phases are merged to reduce the conversion latency. Hence, only four clock cycles are required to perform the 9-bit conversion. The proposed 0.02-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ADC has been fabricated in 90-nm digital CMOS technology. It operates at 50 MS/s and achieves an SNDR of 50.5 dB with a power consumption of 6.9 mW from a 1.0-V supply.

Low-Power and Wide-Bandwidth Cyclic ADC With Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application

In this paper, a power-efficient programmable gain amplifier (PGA) and a cyclic analog-to-digital converter (ADC) are developed for a satellite CMOS image sensor system. The cyclic ADC employs capacitor and opamp reuse techniques to reduce power consumption and occupied silicon area. Moreover, a power-efficient and wide-bandwidth telescopic cascode gain boosting amplifier with capacitive level shifters is adopted to decrease its power consumption further. According to the system specification, a 10-bit, 14-MS/s cyclic ADC with the front-end PGA circuit is implemented in the TSMC 0.18- ?m triple-well 1P3M CMOS image sensor (CIS) process. The proposed cyclic ADC achieves a spurious free dynamic range (SFDR) of 65.1 dB and a signal-to-noise distortion ratio (SNDR) of 52.44 dB with 5-MHz input frequency at 14 MS/s. The power consumption of the cyclic ADC and PGA from a 3.3 V supply are 15.84 mW and 5.78 mW, respectively. The total core area is 0.381 mm2 .

A 1.2 V 4.5 mW 10 bit 8 MS/s cyclic-ADC for mobile video and sensor applications

A 10 bit 8 MS/s cyclic ADC without a dedicated sample and hold is presented. Op-amp sharing and a single ended reference buffer loaded with a resistive divider are used. For power saving the common-mode buffer was replaced by a simple low pass filter. The ADC consumes 4.5 mW and occupies 0.145 mm2. It is fabricated in a 130 nm 1.2 V CMOS process and achieves 57 dB SNDR for an 11 MHz input. The cyclic stage works with a 40 MHz clock which can be increased to 65 MHz where the effective number of bits is reduced to 8. A novel dynamic current switching technique is introduced to reduce the power consumption by 20%. The figure of merit (FOM) is about 0.37 pJ/conversion step.

A High-Speed Low-Noise CMOS Image Sensor With 13-b Column-Parallel Single-Ended Cyclic ADCs

A high-performance CMOS image sensor (CIS) with 13-b column-parallel single-ended cyclic ADCs is presented. The simplified single-ended circuits for the cyclic ADC are squeezed into a 5.6-mum-pitch single-side column. The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB. An ultralow vertical fixed pattern noise of 0.1 erms - is attained by a digital CDS technique, which performs A/D conversion twice in a horizontal scan period (6 mus). The implemented CIS with 0.18-mum technology operates at 390 frames/s and has 7.07-V/lx middots sensitivity, 61- muV/e- conversion gain, 4.9-erms - read noise, and less than 0.4 LSB differential nonlinearity.

A Rail-to-Rail Input 12b 2 MS/s 0.18 μm CMOS Cyclic ADC for Touch Screen Applications

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 ㎷ without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a 0.18 ㎛ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 ㎑ fullscale input at 2 MS/s. The ADC with an active die area of 0.12 ㎟ consumes 3.6 ㎽ at 2 MS/s and 3.3 V (analog)/1.8 V (digital).