Custom VLSI Research Articles

Hardware Implementation of Digital Operational Low Power Units in FPGA

The results of experiments on hardware implementation of various VHDL models of operating devices in FPGA oriented to reducing power consumption are described. Operating devices are also called finite state machines with data paths. It is established that the VHDL model based on clock gating, which is most effective for custom VLSI, can not be implemented in FPGA. Effective models for FPGA are VHDL models based on zeroing unused operands or storing their values in additional memory registers. After conducting an experimental comparison of various methods for a specific operating device (or other digital device), the designer can choose a suitable (compromise) method of VHDL description, considering the obtained values of the parameters of power consumption, performance and hard­ware complexity. The article is a direct continuation of the previous article [1], which describes in detail the models under study and presents the results of experiments on hardware implementation of the same operating devices as part of custom CMOS VLSI

Experimental Study of Algorithms for Minimization of Binary Decision Diagrams using Algebraic Representations of Cofactors

BDD (Binary Decision Diagram) is used for technology-independent optimization, performed as the first stage in the synthesis of logic circuits in the design of ASIC (application-specific integrated circuit). BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph is associated with the complete or reduced Shannon expansion formula. Binary decision diagrams with mutually inverse subfunctions (cofac-tors) are considered. We have developed algorithms for finding algebraic representations of cofactors of the same BDD level in the form of a disjunction or conjunction of other inverse or non-inverse cofactors of the same BDD level. The algorithms make it possible to reduce the number of literals by replacing the Shannon expansion formulas with simpler logical formulas and to reduce the number of literals in the description of a system of Boolean functions. We propose to use the developed algorithms for an additional logical optimization of the constructed BDD representations of systems of Boolean functions. Experimental results of the application of the corresponding programs in the synthesis of logic circuits in the design library of custom VLSI CMOS circuits are presented.

VLSI Implmentation of a Fast Kogge-Stone Parallel-Prefix Adder

This paper presents a VLSI implementation of a high speed Kogge-Stone adder (KSA) using 0.18µm process technology. The adder is known to be one of the fastest adder architectures, and this is validated through a comparison with other adder architectures including the standard ripple carry adder and the carry look ahead adder. Furthermore, our KSA adder is also compared with a default optmized adder from the Artisan standard cell library. The adders are compared for bit widths of 8, 16, and 32. The adders are designed using Verilog and synthesized using both front-end and back-end tools, with complete validation and verification stages, including analysis for performance, power, and area. Results show that in terms of performance, KSA results in the lowest propagation delay with almost constant delay for all bit widths, with up to 70% less delay as compared to all other architectures. Area and power penalty is found to also increase by roughly 59%. In terms of energy usage, the KSA adder results in up to 64% less. In the case when speed and energy are critical, this fast and energy efficient KSA adder can be readily integrated into custom VLSI designs.

СБИС для микроэлектронного координатно-чувствительного детектора нового поколения с расширенным полем анализа для масс-спектрометрии

The authors have developed a custom VLSI chip for the new generation of MCSD devices — multichip detectors with an extended analysis field and higher technical characteristics, which can be used in elemental analysis devices to simultaneously determine the elements that make up the material with high sensitivity and accuracy in real time. VLSI chip contains 384 channels with a spatial resolution of 25 microns has been integrated onto a single chip, each channel has a metal anode to collect the electrons as they emerge from the microchannel plate electron multiplier (MCP); a charge sensitive amplifier to produce a digital signal in response to the electron pulse and a 16-bit counter associated with it to accumulate the counts as they arrive and circuitry to read out the data sequentially from all channels in the microcircuit. The VLSI chip is designed according to the design rules standard 1,0 µm CMOS process. The speed of the microcircuit in the counting mode is at least 15 MHz, in the mode of reading information from the counters — more than 10 MHz. The output from the 16-bit counters on the detectors is presented via an 8-bit port and is read into the control electronics sequentially from each counter in turn in low-byte, high-byte order. The circuit has been designed in such a way that an arbitrary number of detector chips may be abutted together on a substrate behind the MCP, allowing for long focal plane detectors to be built, limited only by the size of MCPs available.

Development of Ultra-Fast Silicon Detectors for 4D tracking

In this contribution we review the progress towards the development of a novel type of silicon detectors suited for tracking with a picosecond timing resolution, the so called Ultra-Fast Silicon Detectors. The goal is to create a new family of particle detectors merging excellent position and timing resolution with GHz counting capabilities, very low material budget, radiation resistance, fine granularity, low power, insensitivity to magnetic field, and affordability. We aim to achieve concurrent precisions of ∼ 10 ps and ∼ 10 μm with a 50 μm thick sensor. Ultra-Fast Silicon Detectors are based on the concept of Low-Gain Avalanche Detectors, which are silicon detectors with an internal multiplication mechanism so that they generate a signal which is factor ∼10 larger than standard silicon detectors. The basic design of UFSD consists of a thin silicon sensor with moderate internal gain and pixelated electrodes coupled to full custom VLSI chip. An overview of test beam data on time resolution and the impact on this measurement of radiation doses at the level of those expected at HL-LHC is presented. First I-V and C-V measurements on a new FBK sensor production of UFSD, 50 μm thick, with B and Ga, activated at two diffusion temperatures, with and without C co-implantation (in Low and High concentrations), and with different effective doping concentrations in the Gain layer, are shown. Perspectives on current use of UFSD in HEP experiments (UFSD detectors have been installed in the CMS-TOTEM Precision Protons Spectrometer for the forward physics tracking, and are currently taking data) and proposed applications for a MIP timing layer in the HL-LHC upgrade are briefly discussed.

A Random Linear Network Coding Accelerator in a 2.4GHz Transmitter for IoT Applications

Random linear network coding (RLNC) is an emerging coding technique, which can provide several advantages in wireless networks, such as throughput gains, increased data robustness, and better utilization of network resources. In this paper, we present the first custom VLSI implementation of RLNC, integrated with an ultralow-power 2.4-GHz transmitter. We examine its energy efficiency and error recovery performance in the context of Internet of Things applications, and we perform experiments quantifying its benefits when it operates separately and jointly with physical layer forward error correction (FEC) codes, as a joint channel and network coding scheme. The chip is fabricated in a 65-nm CMOS process, occupies $2 \times 1.3 ~{\mathrm{ m}}{\mathrm{ m}}^{2}$ and consumes 580 pJ/bit for processing and transmitting data at 1 Mbps. The digital packet processor and encoder occupies $200\times 200 ~\mu {\mathrm{ m}}^{2}$ , consists of an on-chip memory, a multi-rate convolutional encoder, and a RLNC accelerator with configurable redundancy, and consumes $15\mu \text{W}$ , operating at 0.4 V. For improved spectral efficiency, an on-chip pulse shaping filter is implemented, reducing side lobes by 28 dB while consuming $15\mu \text{W}$ . According to our over-the-air experiments, RLNC can provide an effective SNR improvement of 5.6 dB when combined with FEC rate 1/2, and 3.4 dB without FEC, at a packet error rate of $10^{-2}$ .

Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

This paper propose a Virtual-Field Programmable Gate Array (V-FPGA) architecture that allows direct access to its configuration bits to facilitate hardware evolution, thereby allowing any combinational or sequential digital circuit to be realized.
 By using the V-FPGA, this paper investigates two possible ways of making evolutionary hardware systems more scalable: by optimizing the system’s genetic algorithm (GA); and by decomposing the solution circuit into smaller, evolvable sub-circuits. GA optimization is done by: omitting a canonical GA’s crossover operator (i.e. by using a 1+λ algorithm); applying evolution constraints; and optimizing the fitness function. 
 A noteworthy contribution this research has made is the in-depth analysis of the phenotypes’ CPs. Through analyzing the CPs, it has been shown that a great amount of insight can be gained into a phenotype’s fitness.
 We found that as the number of columns in the Cartesian Genetic Programming array increases, so the likelihood of an external output being placed in the column decreases. Furthermore, the number of used LEs per column also substantially decreases per added column.
 Finally, we demonstrated the evolution of a state-decomposed control circuit. It was shown that the evolution of each state’s sub-circuit was possible, and suggest that modular evolution can be a successful tool when dealing with scalability.

Area minimization of regular structures based on solving logical equations

The problem of area minimization of regular matrix structures in custom VLSI circuits using simple folding is considered. A method for solving the key simple folding issue, i.e., implementability testing of a folding set consisting of pairs of mutually foldable columns (rows), is proposed. It is shown how the problem of implementability analysis of the folding set may be reduced to solving a logical equation and the problem of finding roots of the equation to the known problem of satisfiability testing of a conjunctive normal form.

VLSI Wavelet Based Denoising of PPG Signal

Wavelet denoising represents a common preprocessing step for several biomedical applications exposing low SNR. These applica- tions require real time processing along with minimization of power and area, only custom VLSI implementations can be adopted for this fulfillment. In this paper, Photoplethysmography (PPG) signal is used as a biomedical signal as an example. PPG is a non-invasive method in which relative blood volume changes in the blood close to skin is measured. The “pulse waveform” never underwent intensive investigation. Active investigation efforts are opening to reveal its effectiveness beyond oxygen saturation and determination of heart rate. With the introduction of pulse oximeter, this is one of the important waveforms that are normally dis- played in the clinical settings nowadays. But, the acquired PPG signal using PPG sensors are usually corrupted with different kinds of interference like Motion Artifacts, Power Line Noise, etc. We consider Power Line Noise for the performance evaluation of VLSI Wavelet based denoising of PPG signal. Different kinds of Wavelets such as db4, Coif1, Haar for denoising. Also, standard deviation and mean absolute deviation are used as evaluation criteria. Xilinx System Generator for DSP is exploited for the design of the architecture and simulation of proposed denoising method.

A VLSI DSP DESIGN AND IMPLEMENTATION OF COMB FILTER USING UN-FOLDING METHODOLOGY

In signal processing, a comb filter adds a delayed version of a signal to itself, causing constructive and destructive interference. Comb filters are used in a variety of signal processing applications that is Cascaded Integrator-Comb filters, Audio effects, including echo, flanging, and digital waveguide synthesis and various other applications. Comb filter when implemented has lower through-put as the sample period can not be achieved equal to the iteration bound because node computation time of comb filter is larger than the iteration bound. Hence throughput remains less. This paper present the comb filter using one of the methodology needed to design custom or semi custom VLSI circuits named as Un-Folding which increases the throughput of the comb filter. Un-Folding is a transformation technique that can be applied to a DSP program to create a new program describing more than one iteration of the original program. It can unravel hidden con-currency in digital signal processing systems described by DFGs. Therefore, unfolding has been used for the sample period reduction of the comb filter for its higher throughput.

2D space–time wave-digital multi-fan filter banks for signals consisting of multiple plane waves

Two dimensional space---time fan filters may be used for the highly-selective enhancement of spatio-temporal plane-waves on the basis of their directions of arrival. Unlike uniform bandwidth beam filters, ideal fan filters transmit passband signals over a range of directions of arrival that is independent of their 1D temporal spectrum. In this work, closed-form 2D wave-digital filter design equations and corresponding hardware architectures are proposed for realizing M independent fan-shaped passbands having independently steerable directionality and selectivity. A design method based on LCR ladder networks is proposed and implemented using a 2D time-multiplexed raster-scanned architecture that is suitable for low frequency applications such as audio, multimedia, seismic and ultrasonic beamforming. The architectures are designed, simulated, physically realized and tested on FPGA-based prototypes. Examples of 2D IIR M-fan filterbanks with FPGA implementations, together with measured results from on-chip hardware verifications, show the successful design and hardware realization. The filterbanks and hardware architectures are shown to be suitable for real-time sensor-array beamforming applications using custom VLSI circuits.

Comparison between Frame-Constrained Fix-Pixel-Value and Frame-Free Spiking-Dynamic-Pixel ConvNets for Visual Processing

Most scene segmentation and categorization architectures for the extraction of features in images and patches make exhaustive use of 2D convolution operations for template matching, template search, and denoising. Convolutional Neural Networks (ConvNets) are one example of such architectures that can implement general-purpose bio-inspired vision systems. In standard digital computers 2D convolutions are usually expensive in terms of resource consumption and impose severe limitations for efficient real-time applications. Nevertheless, neuro-cortex inspired solutions, like dedicated Frame-Based or Frame-Free Spiking ConvNet Convolution Processors, are advancing real-time visual processing. These two approaches share the neural inspiration, but each of them solves the problem in different ways. Frame-Based ConvNets process frame by frame video information in a very robust and fast way that requires to use and share the available hardware resources (such as: multipliers, adders). Hardware resources are fixed- and time-multiplexed by fetching data in and out. Thus memory bandwidth and size is important for good performance. On the other hand, spike-based convolution processors are a frame-free alternative that is able to perform convolution of a spike-based source of visual information with very low latency, which makes ideal for very high-speed applications. However, hardware resources need to be available all the time and cannot be time-multiplexed. Thus, hardware should be modular, reconfigurable, and expansible. Hardware implementations in both VLSI custom integrated circuits (digital and analog) and FPGA have been already used to demonstrate the performance of these systems. In this paper we present a comparison study of these two neuro-inspired solutions. A brief description of both systems is presented and also discussions about their differences, pros and cons.

The use of parameter optimization in the design of VLSI library cells and custom interfaces of nanoelectronic devices

The modified Levenberg-Marquardt algorithm applied to the parametric optimization of VLSI library cells and custom interfaces of nanoelectronic devices is presented.

Spanning trees set synthesis algorithm for custom VLSI global routing

In this paper, we study the problem of multi-terminal nets layout optimization. To solve the problem, we propose a polynomial-time algorithm, which first constructs minimum spanning tree and then generates spanning tree set. An algorithm for near-minimum spanning trees set with controllable length deviation from a minimum is proposed. Effective trees length deviation value and trees number are investigated.

Reducing the Multiplier-Complexity of Massively Parallel Polyphase 2D IIR Broadband Beam Filters

The superior broadband performance of 2D IIR frequency-planar beam filters, relative to conventional 2D FIR true-time-delay beamforming, has recently been reported using computational electromagnetics and real-time emulations on an antenna test range, resulting in significant improvements of bit-error-rates (BERs) in the presence of broadband interference. Further, massively parallel systolic VLSI circuit polyphase architectures have also been reported (Madanayake et al. in Int. J. Circuit Theory Appl. 2010) for the case of the direct-form signal flow graph (SFG) architecture, operating at a maximum throughput of M-(antenna)-frames-per-clock-cycle (MFPCC). The superior broadband performance of 2D IIR frequency-planar beam filters is extended here from the direct-form signal flow graph (SFG) architecture (Madanayake et al. in Int. J. Circuit Theory Appl. 2010) to the novel differential-form SFG architecture in order to reduce overall complexity. The proposed method employs a differential-form polyphase 2D IIR frequency-planar beam SFG, and a corresponding circuit architecture, to implement the required input-output 2D space-time difference equation. The resultant digital hardware has the significant advantage of much-reduced multiplier complexity, relative to the direct-form structure. For example, when look-ahead pipelining is not employed and for polyphase architectures having two, three, and four phases, the corresponding reductions in multiplier complexity are 20%, 28.6% and 33.3%, respectively. A proof-of-concept prototype circuit is designed and implemented on a Xilinx Sx35 FPGA device for the two-phase case, operating at a frame-rate of 132 million linear frames per second on the uniform linear array (ULA), corresponding to 2-frames-per-clock-cycle at a circuit clock frequency of 66 MHz. The circuit is optimized for low critical path delays (CPDs) using look-ahead pipelining of order three. For ultra-wideband (UWB) radio-frequency (RF) implementations, in such fields as radio astronomy, radar and wireless communications, custom VLSI versions of the proposed circuits are required.

A multichannel compact readout system for single photon detection: Design and performances

Optimal exploitation of Multi Anode PhotoMultiplier Tubes (MAPMT) as imaging devices requires the acquisition of a large number of independent channels; despite the rather wide demand, on-the-shelf electronics for this purpose does not exist. A compact independent channel readout system for an array of MAPMTs has been developed and tested [1,2]. The system can handle up to 4096 independent channels, covering an area of about 20 × 20 cm 2 with pixel size of 3 × 3 mm 2 , using Hamamatsu H-9500 devices. The front-end is based on a 64 channels VLSI custom chip called MAROC, developed by IN2P3 Orsay (France) group, controlled by means of a Field Programmable Gate Array (FPGA) which implements configuration, triggering and data conversion controls. Up to 64 front-end cards can be housed in four backplanes and a central unit collects data from all of them, communicating with a control Personal Computer (PC) using an high speed USB 2.0 connection. A complete system has been built and tested. Eight Flat MAPMTs (256 anodes Hamamatsu H-9500) have been arranged on a boundary of a 3 × 3 matrix for a grand total of 2048 channels. This detector has been used to verify the performances of a focusing aerogel RICH prototype using an electron beam at the Frascati (Rome) INFN National Laboratory Beam Test Facility (BTF) during the last week of January 2009. Data analysis is ongoing: the first results are encouraging, showing that the Cherenkov rings are well identified by this system.

Pipelining saturated accumulation

Aggressive pipelining and spatial parallelism allow integrated circuits (e.g., custom VLSI, ASICs, and FPGAs) to achieve high throughput on many digital signal processing applications. However, cyclic data dependencies in the computation can limit parallelism and reduce the efficiency and speed of an implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. We show how to reformulate saturated addition as an associative operation so that we can use a parallel-prefix calculation to perform saturated accumulation at any data rate supported by the device. This allows us, for example, to design a 16-bit saturated accumulator which can operate at 280 MHz on a Xilinx Spartan-3(XC3S-5000-4) FPGA, the maximum frequency supported by the component's DCM.

Vertex detection in a stack of Si-drift detectors for high resolution gamma-ray imaging

Usually the position resolution in imaging applications with gamma rays is limited due to the range of secondary reaction products to a few mm. Here a new approach will be presented using the vertex of the gamma interaction as the quantity for position measurement. Because the dominant interaction is the Compton effect the vertex detection method as used in particle physics needs a number of essential modifications. Therefore a detector system is investigated consisting of a stack of Si-drift detectors for the vertex detection of the first Compton interaction and a secondary absorption detector where the position of the scattered photon is detected. A number of effects and possible solutions will be discussed including depth of interaction measurement and track reconstruction of the Compton electron which yields useful information. Another very promising approach of measuring the track projection as in a TPC (Time Projection Chamber) will be presented including first successful measurements in a gas detector. Because the expected rate in the first and second detector is of the order of 1 MHz and 10 MHz respectively the concept of read out electronics and data processing based on VLSI custom chips for signal shaping and first buffering and digital pipe-line processors based on FPGAs is presented. Finally a full system for small animal imaging based on the principle of a Compton Camera will be discussed in terms of achievable resolution and sensitivity.

Custom Logic: A Toolkit for the Design of VLSI Custom Control MOS Logic

The Custom Logic toolkit for the design of VLSI custom control MOS array logic is described. The design phases supported range from the generation of behavioral and structural descriptions in high-level languages to mask-layout synthesis.

The CDF Silicon Vertex Trigger

The Collider Detector at Fermilab (CDF) experiment's Silicon Vertex Trigger (SVT) is a system of 150 custom 9U VME boards that reconstructs axial tracks in the CDF silicon strip detector in a 15 μs pipeline. SVT's 35 μm impact parameter resolution enables CDF's Level 2 trigger to distinguish primary and secondary particles, and hence to collect large samples of hadronic bottom and charm decays. We review some of SVT's key design features. Speed is achieved with custom VLSI pattern recognition, linearized track fitting, pipelining, and parallel processing. Testing and reliability are aided by built-in logic state analysis and test-data sourcing at each board's input and output, a common interboard data link, and a universal “Merger” board for data fan-in/fan-out. Speed and adaptability are enhanced by use of modern FPGAs.