Abstract
The Collider Detector at Fermilab (CDF) experiment's Silicon Vertex Trigger (SVT) is a system of 150 custom 9U VME boards that reconstructs axial tracks in the CDF silicon strip detector in a 15 μs pipeline. SVT's 35 μm impact parameter resolution enables CDF's Level 2 trigger to distinguish primary and secondary particles, and hence to collect large samples of hadronic bottom and charm decays. We review some of SVT's key design features. Speed is achieved with custom VLSI pattern recognition, linearized track fitting, pipelining, and parallel processing. Testing and reliability are aided by built-in logic state analysis and test-data sourcing at each board's input and output, a common interboard data link, and a universal “Merger” board for data fan-in/fan-out. Speed and adaptability are enhanced by use of modern FPGAs.
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