Custom Complementary Metal Oxide Semiconductor Research Articles

An Online Course Content for Undergraduate Students on Full-Custom Design of a Digital VLSI Circuit Using Open-Source Software

The Very Large-Scale Integration (VLSI) circuit design is a promising field for undergraduate students hoping to explore job opportunities in electronics circuit design companies. Therefore, several institutes in India offer VLSI courses to electronics engineering undergraduate students. In recent times, because of the pandemic, online classes appeared as an effective method of teaching; this helped in running of academic schedule smoothly without hampering the students’ learning process. In this paper online teaching content is presented to help the student learn digital VLSI circuit design using an open-source tool. This course content is particularly helpful in understanding the theoretical and practical design of a Complementary Metal Oxide Semiconductor (CMOS)-based logic function, with minimal effort by the faculty without access to campus software. The content starts with a digital logic function and its switch-level representation into PULL-UP and PULL-DOWN networks. Then the switch-level circuit with the help of Euler’s graph is translated into a stick diagram and then converted into a layout cell using the lambda design rule. An interesting approach to choosing the gate sequence in the stick diagram from Euler’s graph, and the simulation result of the layout cell are presented and discussed. The approach helped the students in understanding full custom CMOS logic function design, test, and validation, with less effort and time. The survey shows that 86% of the students were satisfied with the content and that the course content helped to achieve an 81% average pass percentage in the two online semesters.

Quantitative Evaluation of Bone Microstructure using High-Resolution Extremity Cone-Beam CT with a CMOS Detector.

A high-resolution cone-beam CT (CBCT) system for extremity imaging has been developed using a custom complementary metal-oxide-semiconductor (CMOS) x-ray detector. The system has spatial resolution capability beyond that of recently introduced clinical orthopedic CBCT. We evaluate performance of this new scanner in quantifying trabecular microstructure in subchondral bone of the knee. The high-resolution scanner uses the same mechanical platform as the commercially available Carestream OnSight 3D extremity CBCT, but replaces the conventional amorphous silicon flat-panel detector (a-Si:H FPD with 0.137 mm pixels and a ~0.7 mm thick scintillator) with a Dalsa Xineos3030 CMOS detector (0.1 mm pixels and a custom 0.4 mm scintillator). The CMOS system demonstrates ~40% improved spatial resolution (FWHM of a ~0.1 mm tungsten wire) and ~4× faster scan time than FPD-based extremity CBCT (FPD-CBCT). To investigate potential benefits of this enhanced spatial resolution in quantitative assessment of bone microstructure, 26 trabecular core samples were obtained from four cadaveric tibias and imaged using FPD-CBCT (75 μm voxels), CMOS-CBCT (75 μm voxels), and reference micro-CT (μCT, 15 μm voxels). CBCT bone segmentations were obtained using local Bernsen's thresholding combined with global histogram-based pre-thresholding; μCT segmentation involved Otsu's method. Measurements of trabecular thickness (Tb.Th), spacing (Tb.Sp), number (Tb.N) and bone volume (BV/TV) were performed in registered regions of interest in the segmented CBCT and μCT reconstructions. CMOS-CBCT achieved noticeably improved delineation of trabecular detail compared to FPD-CBCT. Correlations with reference μCT for metrics of bone microstructure were better for CMOS-CBCT than FPD-CBCT, in particular for Tb.Th (increase in Pearson correlation from 0.84 with FPD-CBCT to 0.96 with CMOS-CBCT) and Tb.Sp (increase from 0.80 to 0.85). This improved quantitative performance of CMOS-CBCT is accompanied by a reduction in scan time, from ~60 sec for a clinical high resolution protocol on FPD-CBCT to ~17 sec for CMOS-CBCT. The CMOS-based extremity CBCT prototype achieves improved performance in quantification of bone microstructure, while retaining other diagnostic capabilities of its FPD-based precursor, including weight-bearing imaging. The new system offers a promising platform for quantitative imaging of skeletal health in osteoporosis and osteoarthritis.

Design and characterization of a package-less hybrid PDMS-CMOS-FR4 contact-imaging system for microfluidic integration.

We demonstrate a hybrid "package-less" polydimethylsiloxane (PDMS)-complementary-metal-oxide-semiconductor (CMOS)-FR4 system for contact imaging. The system embeds the CMOS image sensor directly in a PDMS layer instead of the standard chip package to support microfluidic structures much larger and more complex than those in prior art. The CMOS/PDMS layer is self-aligned to form a continuous, flat surface to provide structural support for upper microfluidic layers. The system consists of five layers of PDMS implementing fluid channels, valves, chambers, and inlets/outlets. A custom CMOS image sensor with integrated signal conditioning circuits directly captures light from sample fluid for high optical collection efficiency. Owing to the flexibility afforded by the integration process, the system demonstrates, for the first time, integrated valves in contact imaging. Moreover, we present the first direct comparison of the optical performance of a CMOS image sensor and a photomultiplier tube (PMT) in identical contact-imaging conditions. Measurements show that our CMOS sensor achieves 17 dB better signal-to-noise ratio (SNR) compared to a commercial PMT across a broad range of integration times, with a maximum SNR of 47 dB. Chemiluminescent testing successfully shows signal detection for different analyte concentrations and integration times. The contact-imaging system demonstrates a detection limit of 25 μM of a 9,10-diphenylanthracene-based solution.

Monolithic ultrasound fingerprint sensor

This paper presents a 591×438-DPI ultrasonic fingerprint sensor. The sensor is based on a piezoelectric micromachined ultrasonic transducer (PMUT) array that is bonded at wafer-level to complementary metal oxide semiconductor (CMOS) signal processing electronics to produce a pulse-echo ultrasonic imager on a chip. To meet the 500-DPI standard for consumer fingerprint sensors, the PMUT pitch was reduced by approximately a factor of two relative to an earlier design. We conducted a systematic design study of the individual PMUT and array to achieve this scaling while maintaining a high fill-factor. The resulting 110×56-PMUT array, composed of 30×43-μm2 rectangular PMUTs, achieved a 51.7% fill-factor, three times greater than that of the previous design. Together with the custom CMOS ASIC, the sensor achieves 2 mV kPa−1 sensitivity, 15 kPa pressure output, 75 μm lateral resolution, and 150 μm axial resolution in a 4.6 mm×3.2 mm image. To the best of our knowledge, we have demonstrated the first MEMS ultrasonic fingerprint sensor capable of imaging epidermis and sub-surface layer fingerprints.

Improved wireless power pickup efficiency using CMOS synchronous rectifier with embedded shorting control

In this work, a shorting control (SC) scheme is integrated into a complementary metal-oxide-semiconductor (CMOS) synchronous rectifier for the output voltage regulation of a wireless power supply. The rectifier is designed to operate in a parallel tuned pickup with a 500 mW output power capability for biomedical implants. Without any additional components, the proposed SC method enables the power pickup to operate with high efficiency under variable coupling conditions while maintaining the required load power to keep the output voltage constant. Desired operating conditions are achieved with increased power transfer capability at weak magnetic coupling conditions and higher power efficiency at strong coupling. A novel derivation describes the change in efficiency with SC duty ratio. Experimental validation is completed with an original custom CMOS integrated rectifier with embedded SC. It is demonstrated that the proposed SC method can increase the overall secondary pickup power transfer efficiency by 14% as the magnetic coupling increases to the stronger end.

Modular Printed Circuit Boards for Broadband Characterization of Nanoelectronic Quantum Devices

We report on the development of a modular system of high-frequency printed circuit boards (PCBs) for electrical low-noise characterization of multigate quantum devices. The whole measurement setup comprises PCBs operating from room temperature to a few kelvins, and custom software to control the broadband electronics held at cryogenic and room temperature. The PCBs coupling scheme and the custom tailoring of the user panel make our platform particularly flexible. At the cryogenic stage, one board hosts the electronics for readout. It consists in a custom complementary metal–oxide–semiconductor circuit for the current sensing. It is composed by a multiplexer for a digital selection of the device under test among up to four samples, connected to a cryogenic transimpedance amplifier with two possible gains, the maximum bandwidth of 250 kHz and the minimum equivalent input noise of 10 fA/ $\sqrt {\mathrm{Hz}}$ . Such board is coupled to the PCB sample holder, where 14 low-frequency input lines bias the devices and control the gates. Four additional high-frequency input paths with a bandwidth of 1 GHz and an isolation lower than −40 dB at 3 GHz have been implemented to apply a few millivolt pulses with a minimum duration of 1 ns. The PCBs assemblage and the cryogenic electronics are electrically characterized at 4.2 K and later used to perform quantum transport spectroscopy and single-charge dynamics readout at a few microsecond scales in two silicon nanoscaled field-effect transistors.

A Highly Sensitive Multi-element HgCdTe e-APD Detector for IPDA Lidar Applications

An HgCdTe electron avalanche photodiode (e-APD) detector has been developed for lidar receivers, one application of which is integrated path differential absorption lidar measurements of such atmospheric trace gases as CO2 and CH4. The HgCdTe APD has a wide, visible to mid-wave-infrared, spectral response, high dynamic range, substantially improved sensitivity, and an expected improvement in operational lifetime. A demonstration sensor-chip assembly consisting of a 4.3 μm cutoff HgCdTe 4 × 4 APD detector array with 80 μm pitch pixels and a custom complementary metal–oxide–semiconductor readout integrated circuit was developed. For one typical array the APD gain was 654 at 12 V with corresponding gain normalized dark currents ranging from 1.2 fA to 3.2 fA. The 4 × 4 detector system was characterized at 77 K with a 1.55 μm wavelength, 1 μs wide, laser pulse. The measured unit gain detector photon conversion efficiency was 91.1%. At 11 V bias the mean measured APD gain at 77 K was 307.8 with σ/mean uniformity of 1.23%. The average, noise-bandwidth normalized, system noise-equivalent power (NEP) was 1.04 fW/Hz1/2 with a σ/mean of 3.8%. The measured, electronics-limited, bandwidth of 6.8 MHz was more than adequate for 1 μs pulse detection. The system had an NEP (3 MHz) of 0.4 fW/Hz1/2 at 12 V APD bias and a linear dynamic range close to 1000. A gain-independent quantum-limited SNR of 80% of full theoretical was indicative of a gain-independent excess noise factor very close to 1.0 and the expected APD mode quantum efficiency.

CMOS-Controlled Color-Tunable Smart Display

We demonstrate a color-tunable smart display system based on a micropixelated light-emitting diode <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(\mu\hbox{LED})$</tex></formula> array made from one InGaN epitaxial structure with high (0.4) indium mole fraction. When integrated with custom complementary metal–oxide–semiconductor (CMOS) electronics and a CMOS driving board with a field-programmable gate array (FPGA) configuration, this <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{LED}$</tex></formula> device is computer controllable via a simple USB interface and is capable of delivering programmable dynamic images with emission colors changeable from red to green by tailoring the current densities applied to the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{LED}$</tex></formula> pixels. The color tunability of this CMOS-controlled device is attributed to the competition between the screening of piezo-electric field and the band filling effect. Comparable brightness of the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{LED}$</tex></formula> pixels emitting at different colors was achieved by adjusting the duty cycle. Further measurement suggests that this microdisplay system can also be used for high-speed visible light communications.

A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

In this paper, we propose a simulation-before-test (SBT) fault diagnosis methodology based on the use of a fault dictionary approach. This technique allows the detection and localization of the most likely defects of open-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS) analog integrated circuits (ICs) interconnects. The fault dictionary is built by simulating the most likely defects causing the faults to be detected at the layout level. Then, for each injected fault, the spectre’s frequency responses and the power consumption obtained by simulation are stored in a table which constitutes the fault dictionary. In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate a considered defect. When testing, the circuit under test is excited with the same stimulus, and the responses obtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full custom CMOS operational amplifier is implemented in 0.25 µm technology and the most likely faults of opencircuit type are deliberately injected and simulated at the layout level.

Experimental characterization of integrated optical wireless components

Line of sight optical links can provide extremely high bandwidth communications between terminals, but in order to maintain alignment between transmitter and receiver, tracking is required. In this letter, we report results from a solid-state tracking transmitter and receiver. The transmitter consists of a custom complementary metal-oxide-semiconductor (CMOS) integrated circuit that is flip-chip bonded to a seven-element resonant cavity light-emitting diode. The receiver uses a custom seven-element InGaAs detector array that is flip-chip bonded to a CMOS integrated circuit. Results from an initial link demonstration show overall system operation at 100 Mb/s/channel, for Manchester coded data.

DEVELOPMENTS AND APPLICATIONS OF HIGH-PERFORMANCE CCD AND CMOS IMAGING ARRAYS

▪ Abstract For over 20 years, charge-coupled devices (CCDs) have dominated most digital imaging applications and markets. Today, complementary metal oxide semiconductor (CMOS) arrays are displacing CCDs in some applications, and this trend is expected to continue. Low cost, low power, on-chip system integration, and high-speed operation are unique features that have generated interest in CMOS arrays. This paper reviews current CCD and CMOS sensor developments and related applications. We compare fundamental performance parameters common to these technologies and describe why the CCD is considered a mature technology, whereas CMOS arrays have significant room for growth. The paper presents custom CMOS pixel designs and related fabrication processes that address performance deficiencies of the CCD in high-performance applications. We discuss areas of development for future CCD and CMOS imagers. The paper also briefly reviews hybrid imaging arrays that combine the advantages of CCD and CMOS, producing better sensors than either technology alone can provide.

Integrated atomic force microscopy array probe with metal–oxide–semiconductor field effect transistor stress sensor, thermal bimorph actuator, and on-chip complementary metal–oxide–semiconductor electronics

A microfabricated 2×1 array of active and self-detecting cantilevers is presented for applications in atomic force microscopy (AFM). The integrated deflection sensor is based on a stress sensing metal–oxide–semiconductor transistor. Full custom complementary metal–oxide–semiconductor amplifiers for signal readout are combined on the same chip. A sensor sensitivity of 2.25 mV/nm, or a change in current ΔId/Id=2.8×10−6/nm, was obtained at the final output stage. Three Al–Si thermal bimorph actuators are integrated on each cantilever for self-excitation and feedback actuation. The efficiencies of the heaters are 2.4–4.7 K/mW. In the experimental setup, a maximum displacement of 8 μm was achieved at 45 mW input. A pair of parallel AFM images in the constant height mode, a typical tapping mode image, and a constant force image with 1.3 μm high features have been successfully taken with the array probe.