Current Starved Ring Oscillator Research Articles

Design and Study the Performance of a CMOS-Based Ring Oscillator Architecture for 5G Mobile Communication

Oscillator circuits are used to make accurate and reliable clock signals for systems as simple as a wristwatch and as complicated as satellites, which are important for long-distance communication. There are many ways to build an oscillator circuit, using either passive or active parts. Each option has pros and cons, but at the current level of mobile communication development, the most important things are interoperability and low power use. This need has driven the development of compact, battery-operated electronics, and Very Large-Scale Integration (VLSI)-based ring oscillators provide the ideal solution. These oscillators ought to dissipate less power, have a large tuning range, and be compact. The paper presents a novel Complementary Metal Oxide Silicon (CMOS) ring oscillator that serves as a Voltage Controlled Oscillator. The suggested architecture utilizes the advantages of both a current-starved ring oscillator and a negative-skewed delay by combining their constituent parts. The proposed architecture has a control voltage of 1.15 V and a supply voltage of 2 V, generating a 9.35 GHz dominant frequency with a 13.82% harmonic distortion between the inputs and outputs. The proposed architecture can implement 5G-based applications that require high frequency and low power by carefully selecting the passive components within the design. Doi: 10.28991/ESJ-2024-08-01-020 Full Text: PDF

True Random Number Generator Based on RRAM-Bias Current Starved Ring Oscillator

True Random Number Generator Based on RRAM-Bias Current Starved Ring Oscillator

Implementation And Comparison of Different Stages of Current Starved CMOS Ring Oscillator – A Study

The ring oscillators serves as the fundamental building blocks in both digital and analog circuit design, as its extensive use is found in various electrical systems, including phase-locked loops, frequency dividers, and clock generators. This study gives a general overview of the ring oscillator circuit, including its workings, uses, and important design considerations. The ring oscillator generates timing signals for synchronous operation and is often employed as a clock generator in digital systems. It may also be used as a frequency divider to separate higher frequencies into lower ones. A closed loop is used to connect an odd number of inverting stages to create the ring oscillator circuit. An inverter, which is often built using complementary metal-oxide-semiconductor (CMOS) technology, is a component of every stage. By adding a delay to each step, the ring oscillator creates a self-sustaining oscillation. The development and comparison of 3, 5, and 7 stage ring oscillators for different performance metrics, as well as corner analysis for propagation delay and the effect of temperature on the operation of the ring oscillator was performed using Cadence Virtuoso with 90nm technology. This comparison of several phases of a current-starved (CS) ring oscillator offers an advantage to the best design with innovation based on the technology employed and outcomes from the corner analysis, which hasn't been done in any of the more recent researches.

Highly Sensitive Wireless NO2 Gas Sensing System

There is a need for reliable and accurate air quality monitoring systems in order to secure human health from the air pollutants such as nitrogen dioxide (NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). The development of low-cost and modern technology-compatible sensing systems is essential. In this work, a highly sensitive and selective Indium Gallium Zinc oxide (IGZO) thin film transistor has been used to design an efficient and wireless NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> sensing system. The sensing system uses the IGZO TFT as a current source for the current-starved ring oscillator where exposed NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> concentration determines the oscillation frequency. The presented NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gas sensing system exhibited excellent sensitivity of 5.39 MHz/ppm with the lowest detection limit (LOD) of 50 ppb at room temperature. To the best of the authors’ knowledge, the achieved sensitivity is the best-reported performance for frequency-based NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> sensors. The sinusoidal output of the sensor obviates the need for costly peripheral signal conditioning circuits and allows direct integration with wireless systems. The 13.56 MHz RFID antenna connected to the output of the sensor is used to show wireless sensing compatibility and highlights the excellent candidacy of the proposed work for the growing Internet of Things (IoT) and untethered sensor applications.

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique

This paper reports a reference-less frequency-detector-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter to maintain quarter-rate operation, supporting a capture range of 110.4%. By the virtue of a deliberate-current-mismatch charge pump pair, we form the single-sided capture scheme in the frequency detection characteristic, eliminating the power-hungry circuits in the high-speed clock and data paths. Employing a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in the overall 32 bands. Prototyped in a 65-nm CMOS, the BBCDR covers a wide data rate from 10.8 to 37.4 Gb/s, achieving an acquisition speed of 4.63 (Gb/s)/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> s and an energy efficiency of 1.3 pJ/bit.

A Fault-Tolerant Current-Starved Ring Oscillator With Signal-Flip Protection Delay Cells Against Radiation Effects

This brief proposes a fault-tolerant current-starved ring oscillator to provide accurate clock signals against radiation effects. The ring oscillator adopts multiple signal-flip protection delay cells (SPDC) that can prevent unwanted signal flips due to external radiation. The SPDC utilizes input-dependent voltage limiters with delayed switching, maintaining the output voltage level against radiation effects, while minimally affecting normal operations of the delay cell. The proposed ring oscillator with SPDC was fabricated in 180-nm CMOS process and fully verified with chip tests in actual radiation environments. When generating 15 MHz clock signal at 1.8 V supply, the proposed ring oscillator ensures smaller frequency deviation from −5% to 11% with radiation charges of 0.25 pC compared to the conventional ring oscillator which suffers from large deviation from −35% to 79%. The minimum amount of radiation charge that causes >30% frequency deviation was 7.6x improved than conventional clock generators, verifying fault tolerance against large radiation effect.

Implementation of the High Speed PLL

the most multipurpose application of the phase locked loops (PLL) is for clock generation and clockrecovery in microprocessor, networking, communication systems, and digital circuit and frequency synthesizers.Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks inhighperformance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter (deviation) reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with fasterlocking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time.PLL is a mixed signal circuit as itsarchitecture involves both digital and analog signalprocessing units. The present work focuses on the redesign of a PLL system using the 90 nm process technology (GPDK090 library) in EDA TANNER Design Environment.Here a current starved ring oscillator has been considered for its superior performance in form ofits low chip area, low power consumption and wide tunable frequency range. Thesimulation results ofPLL are reported in this work. It is found that the designed PLL consumes 11.68mW power froma 1.8V D.C. supply and have a lock time 280.6 ns. As the voltage controlled oscillator (VCO) isthe heart of the PLL, so the optimization of the VCO circuit is also carried out using the optimization technique. The results of the VCO designed are shown. Keyword: PLL, VCO, GDPK 900, Charge pump (CP).

Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.63\times $ </tex-math></inline-formula> lower minimum power consumption and slightly better FoM values than CSROs.

A Bimodal Low-Power Transceiver featuring a Ring Oscillator-based Transmitter and Magnetic Field-based Receiver for Insertable Smart Pills.

This paper presents a novel bimodal, low-power, mm-scale transceiver for insertable smart pills. The proposed PA-less, 915 MHz uplink transmitter (TX) incorporates an 1.21.2 mm2 on-chip, non-resonated antenna as part of a current-starved ring oscillator (RO) and directly transmits data by turning the RO on/off. This RO-based uplink TX is implemented in 180 nm CMOS along with a power management unit, which generates all internal reference voltages and supplies from a single battery. The uplink TX achieves a data rate of 33 Mb/s and consumes 210 μW, resulting in an energy efficiency of 6.4 pJ/bit. The orientation-insensitive magnetic field-based downlink receiver (RX) is implemented with an external 3-D magnetic sensor, achieves 0.02 kb/s of data rate limited by our measurement setup, and consumes 270 μW. Wireless measurements in saline over 150 cm and prototype of the 3.213.62.3 mm3 insertable pill are presented.

A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS

This brief describes a fully integrated 10-V pulse driver. It comprises a four-stage switched-capacitor voltage multiplier (SCVM) and a dedicated high-voltage output driver (HVOD) with multiband pulse-frequency modulation (MPFM) to generate efficiently 10 V regulated output pulses. Specifically, an analog/digital hybrid-controlled current-starved ring oscillator (HCRO) modulates the switching frequencies at distinct bands to regulate the high-voltage (HV) supply for the HVOD, while enabling fast output transitions with an improved driving efficiency. Prototyped in 65-nm bulk CMOS, the driver demonstrates 10-V pulse generations over a 0.1-to-1-MHz range for a 15 pF//50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> load. With the proposed MPFM, this work measures an overall driving efficiency of up to 19.9%, corresponding to a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 1.6\times $ </tex-math></inline-formula> improvement over prior arts. The measured output rise time of 119 ns is also ~25% faster when compared with using the conventional pulse-frequency modulation (PFM) scheme.

Low-Temperature Deep Ultraviolet Laser Polycrystallization of Amorphous Silicon for Monolithic 3-Dimension Integration

Monolithic 3-dimensional integration (M3D) requires heat treatment techniques that should not degrade the device performance of the lower layers when applied to device fabrication in the upper layers. Deep ultraviolet (DUV) laser annealing was implemented in the crystallization of amorphous silicon and source/drain junction activation to fabricate polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect-transistors (MOSFETs) for upper-layer devices. The poly-Si MOSFET devices were fabricated successfully on top of the bottom electronic circuit layer (isolated by a thick silicon dioxide layer). Devices on the upper and lower layers were connected through interlayer vias to form a current-starved ring oscillator. The current-to-frequency converter on the bottom layer showed a reasonable increase in frequency as the current of the poly-Si MOSFET on the upper layer increased with increasing silicon grain size, confirming that DUV laser annealing did not degrade the performance of the bottom layer devices. This opens more opportunities for using DUV laser annealing in the M3D integration.

Comparative Study and Design of Current Starved Ring Oscillators in 16 nm Technology

In this brief, different characteristics of current starved ring oscillator (CSRO) circuits are investigated and four new designs are proposed. A new parameter, known as phase noise bandwidth product (PNBP), is also proposed to address the trade-off between phase noise performance and frequency tuning range while designing ring oscillators (ROs). The proposed circuits are compared with existing architectures in terms of power consumption, frequency bandwidth, maximum frequency, phase noise, power delay product (PDP) and PNBP. For performance evaluation, three-stage CSROs have been implemented in Cadence software using the 16 nm PTM High Performance (HP) technology model. Simulation results demonstrate that two newly proposed CSRO architectures using one NMOS sink or one PMOS source have similar optimum results in terms of PDP and PNBP as the existing CSRO using an output switch scheme, but with an advantage of lower area requirement. Moreover, all four proposed architectures show improved performance in terms of PDP and PNBP compared to conventional CSRO. The performance of the CSROs is also observed and compared with respect to the variations in process-voltage-temperature (PVT) parameters.

Performance evaluation of CCOs for the optimization of low-power pressure-based implantable wireless systems

Implantable biomedical devices intended for remote follow-up of Cardiovascular Diseases (CVD) are often based on MEMS pressure sensors and the corresponding CMOS electronics, which are responsible for powering, signal conditioning and data transmission. This kind of heterogeneous systems achieves reduced dimensions and consumption by monolithic integration on the same silicon substrate. The objective of this work is to analyze and fully characterize several Capacitor-Controlled Oscillator (CCO) topologies that can be used for the aforementioned implantable applications, by comparison of their most relevant performance parameters. The results will allow the design optimization of low-power wireless implants, aimed at a future development of embedded systems with real-time data acquisition. Five topologies have been chosen for the evaluation: a standard ring oscillator; a current-starved ring oscillator; a Lee-Kim fully-differential oscillator; a coupled Sawtooth oscillator, and a modified Sawtooth oscillator designed for CCOs biased by a ramped voltage signal. Comprehensive simulations allowed the estimation of the output frequency, percentage tuning range, maximum linearity error, phase noise and power consumption for each design, as well as a Figure of Merit, for every CCO. For the calculation of these performance metrics, the impact of biasing circuits and different tuning strategies has also been considered.

A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM.

A high-voltage generator (HVG) is an essential part of a radio frequency identification electrically erasable programmable read-only memory (RFID–EEPROM). An HVG circuit is used to generate a regulated output voltage that is higher than the power supply voltage. However, the performance of the HVG is affected owing to the high-power dissipation, high-ripple voltage and low-pumping efficiency. Therefore, a regulator circuit consists of a voltage divider, comparator and a voltage reference, which are respectively required to reduce the ripple voltage, increase pumping efficiency and decrease the power dissipation of the HVG. Conversely, a clock driving circuit consists of the current-starved ring oscillator (CSRO), and the non- overlapping clock generator is required to drive the clock signals of the HVG circuit. In this study, the Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed that the designed CSRO dissipated only 4.9 μW at 10.2 MHz and that the phase noise was only -119.38 dBc/Hz at 1 MHz. Moreover, the proposed charge pump circuit was able to generate a maximum VPP of 13.53 V and it dissipated a power of only 31.01 μW for an input voltage VDD of 1.8 V. After integrating all the HVG modules, the results showed that the regulated HVG circuit was also able to generate a higher VPP of 14.59 V, while the total power dissipated was only 0.12 mW with a chip area of 0.044 mm2. Moreover, the HVG circuit produced a pumping efficiency of 90% and reduced the ripple voltage to <4 mV. Therefore, the integration of all the proposed modules in HVG ensured low-ripple programming voltages, higher pumping efficiency, and EEPROMs with lower power dissipation, and can be extensively used in low-power applications, such as in non-volatile memory, radiofrequency identification transponders, on-chip direct current DC-DC converters.

A Low-Power Sensitive Integrated Sensor System for Thermal Flow Monitoring

Thermal-based flow monitoring has found widespread applications due to its noncontact measurement, high sensitivity, low flow resistance, miniaturization, ease of integration, and low-power consumption. In this work, a low-cost and affordable inkjet-printed graphene-based thermal sensor is integrated with a low-power CMOS circuit for flow rate monitoring. The custom inkjet-printed sensor consists of a silver nanoparticle interdigitated pattern with a coating of graphene, all printed on a glossy photo-paper substrate. The sensor read-out circuit is an energy-efficient current-starved ring oscillator. The sensor current controls the bias current of a current-starved ring oscillator and modulates the output frequency. A driver circuit then transforms the output to a square wave pulse signal. The scheme is designed and fabricated using the 0.13- $\mu \text{m}$ standard CMOS process and occupies an area of 1.5 mm $\times1.7$ mm. Test results indicate that the prototype ring oscillator circuit consumes 19– $90~\mu \text{W}$ for an oscillation frequency variation of 517 kHz–6.45 MHz. The output frequency variation with sensor current shows linear performance with ${R}^{2} = 0.9966$ .

Design and performance analysis of wrap-gate CNTFET-based ring oscillators for IoT applications

In recent years, usage of novel non-Si materials as the gate channel region in next generation of field effect transistors, including carbon nanotubes, have been in the spotlight of nanoelectronics research due to astounding carrier transport and I-V characteristics. These properties make them a highly suitable platform in modern radio frequency applications. Therefore, the aim of this work is to design and investigate the performance of current-starved and skewed ring oscillators based on ballistic carbon nanotube transistors (CNTFETs). In this work, we have utilized wrap-gate structure to have a better electrostatics control and mitigate the gate leakage current. All the CNTs in both n-type and p-type transistors have 0.9 nm diameter and an array of CNTs have been exploited in the gate region to achieve low-power and high-performance operation. The simulation results demonstrate that the proposed CNTFET-based ring oscillators have sub-100μW power consumption (Pcurrent-starved = 6.011 μW, Plow-skew = 67.2 μW, and Phigh-skew = 23.5 μW) along with wide frequency tuning range (fcurrent-starved = 0.202 GHz − 1.205 GHz, flow-skew = 0.361 GHz − 2.137 GHz, and fhigh-skew = 0.335 GHz − 2.38 GHz) which are suitable for internet of thing (IoT) devices operating from 100 MHz to 5.8 GHz. Finally, based on the simulation results, we have emphasized that the CNTFET-based skewed ring oscillators are suitable for high-speed purposes, while the CNTFET-based current-starved ring oscillator is recommended for low-power and high-swing applications.

Highly Digital Second-Order $\Delta\Sigma$ VCO ADC

A continuous-time second-order $\Delta \Sigma $ analog-to-digital converter (ADC) is presented in this paper. The proposed ADC is based on a novel architecture and uses current starved ring oscillators as integrators to achieve the second-order noise shaping. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Static element mismatch in the multi-bit current digital-to-analog converter is high-pass shaped by intrinsic data-weighted averaging. Detailed analysis and insights on the various trade-offs involved in the design of the proposed ADC are presented in this paper. A prototype ADC is implemented in 65-nm CMOS and achieves 64.2-dB SNDR at a bandwidth of 2.5 MHz and a Schreier FoM of 158.2 dB. The ADC operates at 205 MHz and consumes 1 mW of power. The measured power supply rejection ratio is 56.2 dB.

A highly linear current-starved VCO based on a linearized current control mechanism

A highly linear voltage controlled oscillator (VCO) suitable for emerging time-based and VCO-based applications is presented. By providing a very linear and high dynamic range biasing current for a current-starved ring-oscillator, improved linearity is achieved over rail-to-rail input control voltage. The input control voltage is first mapped by a resistive network and then is transformed to a biasing current by means of two linear voltage-to-current (V/I) converters with proportional and complementary behavior with respect to the control voltage. The difference between output currents of the V/I converters is utilized to enhance the linearity and frequency tuning range of the VCO. The proposed architecture is very compact and can be employed for most of current-starved ring oscillators regardless of delay element topology. Simulation results with a 1.8-V 0.18-μm standard CMOS technology show that for a rail-to-rail input voltage, the nonlinearity of frequency error using a simple single-ended delay element ranges from 0.02% to 0.9%. By using a differential delay element, the maximum frequency error reduces to 0.66%.

A CMOS MedRadio Transceiver With Supply-Modulated Power Saving Technique for an Implantable Brain–Machine Interface System

A MedRadio 413–419-MHz inductorless transceiver (TRX) for an implantable brain–machine interface (BMI) in a 180 nm-CMOS process is presented. Occupying 5.29 mm2 of die area (including pad ring), this on–off keying (OOK) TRX employs a non-coherent direct-detection receiver (RX), which exhibits a measured in-band noise figure (NF) of 4.9 dB and $S_{11}$ of −13.5 dB. An event-driven supply modulation (EDSM) technique is introduced to dramatically lower the RX power consumption. Incorporating an adaptive feedback loop, this RX consumes 42-/92- $\mu \text{W}$ power from 1.8-V supply at 1/10-kbps data rates, achieving −79/−74-dBm sensitivities for 0.1% bit error rate (BER). The TX employs a current starved ring oscillator with an automatic frequency calibration loop, covering 9% supply voltage variation and 15 °C–78 °C temperature range that guarantees operation within the emission mask. The direct-modulation TX achieves 14% efficiency for a random OOK data sequence at −4-dBm output power. Wireless testing over a 350-cm distance accounting for bio-signal data transfer, multi-user coexistence, and in vitro phantom measurement results is demonstrated.

Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.