Current Saturation Region Research Articles

Current Saturation Behavior in GaN Polarization Superjunction Hybrid Diode

This is the first report on the current saturation behavior observed in the forward characteristics of polarization superjunction (PSJ)‐based hybrid PiN‐Schottky GaN power diodes fabricated on Sapphire. In the current saturation region, most of the applied anode voltage is dropped across the regions immediately adjacent to the edge of the doped P‐GaN region closest to the cathode. This significant potential drop occurs within a short distance, resulting in a high electric field and depletion of electrons, causing the current saturation behavior via velocity saturation in these PSJ hybrid diodes.

Achievable Thrust Expansion Control at Current Saturation of Variable-Pitch Propeller for Drones

On drones, which have become popular in recent years, the installation of variable pitch propellers is being considered and researched for industrial applications such as large drones and flying mobility. A variable-pitch propeller not only provides higher responsiveness than control by rotational speed alone, but also expands the thrust that can be achieved by optimizing the combination of rotational speed and pitch angle. In this paper, it is experimentally verified that, in the current saturation region of a variable-pitch propeller motor, the control method using simple frequency-separated command values for rotational speed and pitch angle causes an inverse response in transient conditions, and we attempt to explain this response by a linearized model including unstable zero. Basing on the model, we proposed a control method in which the pitch angle is controlled by a first-order filter while the maximum current is applied. The proposed method enables control design with a trade-off between initial undershoot and settling time with one parameter. The effectiveness of the proposed method is verified by simulation and experiment.

Trap induced negative differential conductance and back-gated charge redistribution in AlGaN/GaN power devices

Negative differential conductance (NDC) seen in the drain current saturation region is typically attributed to self-heating effects in GaN HEMTs. In this paper, it is demonstrated that NDC is due to trap states in the buffer resulting from poor carrier confinement in the channel during saturation which leads to stray electrons exiting the channel and becoming trapped. Substrate bias testing has been used to confirm that severe current collapse occurs when those electrons are forced to the surface, and that NDC occurs when the carriers are forced to the buffer. In addition to this, pulsed I-V characterization is performed among other tests to isolate the cause of NDC in the saturation region, which effectively eliminated trapping mechanisms that lead to gate- and drain-lag from contributing to NDC. To the best of our knowledge, we are the first to report NDC not as a result of self-heating, but due to trapping within the buffer.

Effect of the Conductive Channel Cut-Off on Operation of n+–n–n+ GaN NW-Based Gunn Diode

Nowadays modern science and technology require development of efficient electromagnetic emitters covering far GHz and THz ranges. Semiconductor elements with negative differential resistance (NDR) such as Gunn diodes based on GaAs and InP are well-established powerful microwave emitters. In this work the Gunn diode structure based on single GaN nanowire with the potential of THz device development was proposed and investigated both theoretically and experimentally. According to the results of the numerical modeling, the Gunn generation can be obtained in the proposed geometry. Dependence of the doping concentration on the NW length necessary for the electrons domain formation was obtained. The nanostructures were grown via molecular beam epitaxy technique. Contacts to single nanowires were fabricated with the combination of e-beam lithography and thermal evaporation. It was shown experimentally that the volt-ampere characteristics of the GaN nanowire structure possess current saturation region. Experimental results correspond well to proposed numerical model.

Photo Sensitivity Enhanced By the Modulation of Oxide Thickness in MIS(p) Structure

It was found that the ratio of light to dark current can be enhanced by coupling effect with simple MIS(p) on concentric MIS structure [1]. Gate with bias can largely decrease dark current, and thereby improve the ratio. In this work, to research deeper about it, the enhancement of ratio with gate voltage is concentrated on the modulation of oxide thickness. The topside and cross section of the studied MIS(p) structure with the concentric pattern is shown in Fig. 1(a). The radius of inner circle r1 is 85um. The space between inner and outer gate, i.e., s, is 20um. The outer radius of the ring is 300um. Here, the inner circle is defined as diode and the outer ring is defined as gate. Also, according to the previous work [1], a specific gate voltage of VX is defined as when it causes the lowest diode dark current in ID-VG curve (the inset in Fig. 1(b)) and therefore exhibits the largest enhanced ratio. Fig. 1(b) a shows I-V curve of light current and dark current with VG=VX in two oxide thickness of 2.5nm and 3nm. The ratio is defined by the light current to dark current at 2.5V which is located at the diode current saturation region. Comparing the ratio of light to dark current in two thickness, it is obvious to show that the ratio is dependent on oxide thickness and MIS structure with a thicker oxide might have a higher ratio. To further study the relation of ratio and thickness, samples with different thickness were explored to examine their light to dark current ratios as shown in Fig. 2(a). From Fig. 2(a), it obviously shows that the ratio is highly increased for thicker oxide. Also, in order to see the effect of illumination, three strength of illumination with 131lux, 306lux, and 410lux were studied. Fig. 2(b) shows that thicker oxide indeed has a higher ratio than thinner counterpart no matter what the strength of illumination is. To analyze the dependency of the saturation current on oxide thickness, the dark current, light current and the ratio of light to dark current are separately presented for various thicknesses as shown in Fig. 3(a). It’s clear to indicate that the dark current reduces with the oxide thickness and light current has no obvious relation with thickness. Hence, the discussion is divided into two parts. To discuss about dark current, Fig. 3(b) demonstrates of the carrier and two currents part of dark diode current from the gate region under VG=VX in dark environment. Because gate voltage is biased in the minimum diode current which is near VFB, minority carrier gathered under gate region is very few. Then, the diffusion current from gate to diode is very small due to the subtle divergence of carrier concentration. Therefore, the diffusion current by coupling effect is largely reduced and contributed less to the barrier height modulation of diode. As a result, diode current is mainly dominated by the injection current part from the gate region. In Fig. 3(c), because the gate current which induces the injection current is strongly dependent on oxide thickness, it implies that thicker sample which has lower injection current has lower saturation current. It confirms that dark current is clearly decreased with increasing thickness under VG=VX in Fig. 3(a). For the light current part, because the light current is also contributed from light-induced electron-hole pairs, the light current is not solely dependent on oxide thickness. Hence, light current does not show similar dependence of thickness. The ratio of light to dark current is largely enhanced by the largely decrease of dark current due to the increase of oxide thickness. Furthermore, the ratio of light to dark current increases with the stronger strength of illumination in the thicker MIS sensor as shown in Fig. 2(b). The result indicates that there is a larger light current in the stronger illumination because of more electron-hole pairs. Therefore, the ratio of light to dark current is increased with the strength of illumination. In conclusion, the modulation of oxide thickness is of importance to the photo sensitivity of MIS(p) tunnel diode. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 105-2221-E-002-180-MY3 and MOST 106-2221-E-002-196-MY3. [1] W.T. Hou and J.G.Hwu*, 2017, “Photo Response Enhancement in MIS(p) Tunnel Diode via Coupling Effect by Controlling Neighboring Device Inversion Level”. Electronic and Photonic Devices and Systems, ECS Journal of Solid State Science and Technology, 6(10), pp. Q143-147, 2017 Figure 1

Hot-carrier-induced current capability degradation and optimization for lateral IGBT on thick SOI substrate

In this paper, the hot-carrier-induced current capability degradation of a 600 V lateral insulated gate bipolar transistor (LIGBT) on thick silicon on insulator (SOI) substrate is investigated. Our experiments found that, for the SOI-LIGBT, the worst stress condition is the maximum gate voltage (Vgmax) condition and the current degradation is dominated by the damages in the channel region under the Vgmax stress condition. However, further analyses show that the influence of channel region damages on the collector current degradation increases with the increase of measured collector voltage and is maximum in the current saturation region. Therefore, in our opinion, the hot-carrier-induced current capability degradation of the SOI-LIGBT should be evaluated by the degradation of saturation current under the Vgmax stress condition. In addition, a novel SOI-LIGBT structure with an external p-type region was also proposed, which can alleviate the damage in the channel region by reducing the lateral electric field peak. Our experimental results demonstrate that the proposed structure could optimize the hot-carrier reliability effectively with the other characteristics maintained.

The Device-Perimeter Dependency in the Transient Current of a Metal-Insulator-Metal-Insulator-Semiconductor Capacitor with Anodic Oxide Films

Capacitors are commonly used in semiconductor devices like gate capacitors of transistors, memory cells of dynamic random access memory (DRAM), and so on. In this work, a capacitor with electrochemically grown thin oxide films was fabricated as shown in figure 1. The Al2O3/Al/AlSixOy/SiO2 stack structure was formed by anodization as shown in figure 2. First, the SiO2 layer was formed by anodizing the surface of a p-type Si wafer as shown in figure 2(a). Next, a thin Al film was thermally deposited. Then, the Al2O3 layer was formed by partially anodizing the surface of the Al film as shown in figure 2(b). The sample was then annealed at 380°C in N2 ambient for 10 min, and an AlSixOy layer was formed between Al and SiO2. Three square device patterns, 150×150μm2 (sample D1), 300×300μm2 (sample D2), and 600×600μm2 (sample D3), of the Al electrodes were fabricated by thermal deposition and lithography. Figure 3 shows the gate current per device-area and per device-perimeter versus the gate voltage of the capacitor. Note that the currents merge at negative voltages in (a) while they merge at the saturation region in (b). It tells that the current flows uniformly across the whole area of the device at negative voltages while it flows along the device edge at the voltages in current saturation region due to the fringing field effect, which coincides with the results in the previous studies [1]. Figure 4 shows the read currents of the capacitor at 0.1 V versus time after various negative and positive voltage pulses. The inset in (a) is the schematic diagram of the write and read processes settings. (b) is the read currents in (a) divided by the device perimeter. Note that the negative read currents merge in (a) while the positive read currents merge in (b). The charge in the sandwiched Al layer and the read current can be written as Qg (t)=Qg (0)exp(–t/τ) (1) Ig (t)=d Qg (t)/dt=–(Qg (0)/τ)exp(–t/τ) (2) where Qg (t) is the stored charge at time t. τ is the time constant which is equal to RsCg . Rs is the total series resistance. Cg is the gate capacitance. The time constants extracted from figure 4 are all about 0.7 s. Qg (0) can be obtained by the write process as follows: Qg (0)≈Qg (–t 0)=∫(I write–I leak)dt (3) where I write is the write current, I leak is the leakage current during writing, and t 0 is the switching time from write to read. While the write voltage is positive, the electrons flow from substrate to the sandwiched Al layer along the device edge due to the fringing field effect. However, the electrons also leak from the sandwiched Al layer to metal gate along the edge due to the thin oxide, and therefore Qg (0) is nearly independent of the device dimension. Hence, Ig (t) is independent of the device dimension. While the write voltage is negative, the stored electrons in the sandwiched Al layer were depleted due to the high negative gate field. When read at 0.1 V, the electrons were injected into the sandwiched Al layer along the edge due to the fringing field effect, and therefore Qg (0) is dependent on the device perimeter. Hence, Ig (t) is proportional to the device perimeter. The device-perimeter dependency in the current characteristics of the capacitor mentioned in this work might be useful for IC circuit design. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. NSC 102-2221-E-002-183-MY3 and MOST 103-2622-E-002-031. Figure Captions: Figure 1. (a) The TEM cross-section and (b) the EDX line-scanning component analysis of the capacitor. Figure 2. The schematic diagrams of (a) SiO2 anodization and (b) Al2O3 anodization processes for the capacitor fabrication. Figure 3. (a) The gate current per device area and (b) the gate current per device perimeter versus gate voltage characteristics. Sample D1, D2, and D3 are the devices with square patterns of 150×150μm2, 300×300μm2, and 600×600μm2. Figure 4. The currents read at 0.1 V versus time after the write processes. The inset in (a) shows the operation process. (b) is the read currents in (a) divided by the device perimeters.

A “proton pump” concept for the investigation of proton transport and anode kinetics in proton exchange membrane fuel cells

A novel concept for the measurement of proton transport properties and electrode kinetics in proton exchange membrane fuel cells (PEMFC) is presented. The “proton pump” is essentially a fuel cell operated with pure nitrogen or very low hydrogen partial pressure instead of oxygen-containing gas on the cathode side, avoiding the complicated electrode kinetics of oxygen reduction. In this first study using this concept, we investigated the proton transport in high temperature PEMFC based on polybenzimidazole (PBI)/phosphoric acid membranes. The impedance spectra of the proton pump allow the clear distinction between anode and cathode kinetics and proton transport in the membrane. Identifying and analyzing the contribution of the anodic processes in the impedance spectra enabled the quantitative investigation of anode kinetics based on the Butler–Volmer equation. The proton transport was investigated in more detail in the current saturation region, where proton transport turned out to be the limiting process in case of sufficient H 2 supply at the anode. The maximum proton transport capacity of the PBI/phosphoric acid membrane was found to be comparable to those of Nafion ® membranes.

Room-temperature plasma waves resonant detection of sub-terahertz radiation by nanometer field-effect transistor

We report on room-temperature, resonant detection of 0.6THz radiation by 250nm gate length GaAs∕AlGaAs heterostructure field-effect transistor. We show that the detection is strongly increased (and becomes resonant) when the drain current increases and the transistor is driven into the current saturation region. We interpret the results as due to resonant plasma wave detection that is enhanced by increasing the electron drift velocity.

A DC model for fully-depleted SOI MOSFETs

An alternative approach for the calculation of the threshold voltage of an SOI MOSFET, taking into account the potential drop in the silicon substrate, is proposed. The approach is extended to short channel devices and improves the predictions of the characteristics of a fully-depleted SOI MOSFET. The current-voltage characteristics are derived by including substrate effect, mobility degradation and channel length modulation in the current saturation region. The theoretical predictions of the model agree with the experimental data available in the literature.

An analytical model for I-V and small-signal characteristics of planar-doped HEMTs

An analytical current-voltage (I-V) model for planar-doped HEMTs is developed. This compact model covers the complete range of I-V characteristics, including the current saturation region and parasitic conduction in the electron-supplying layer. Analytical expressions for the small-signal parameters and current-gain cutoff frequency are derived from the I-V model. Modeling results for a 0.1- mu m-gate planar-doped AlInAs-GaInAs HEMT show excellent agreement with measured characteristics. Threshold voltages and parasitic conduction in planar-doped and uniformly doped HEMTs are also compared and discussed. >

Improved negative feedback technique to reduce drain conductance of GaAs MESFETs for precision analogue ICs

An improved negative feedback technique to reduce the absolute magnitude of the frequency-dependent drain conductance inherent in GaAs MESFETs has been demonstrated for low-threshold (less than ?1 V) devices. The new dual-threshold arrangement guarantees that the primary device of the self-bootstrapping pair operates at the current saturation region without relying on the existence of early saturation. A factor of 11 reduction in the drain conductance was realised. A simple inverter amplifier of identical composite driver and load has demonstrated 21 dB improvement in voltage gain over that using single FETs.

Characteristics of junction field effect devices with small channel length-to-width ratios

The characteristics of junction field effect devices with small channel length-to-width ratios are discussed. For such devices, the junctions deviate significantly from the parallel planar junction case normally considered in the analysis of field effect devices. The spreading of the junction depletion region beyond the ends of the gate junctions becomes important. A model is developed for calculating the shape of the junction depletion region including circular gate geometries near the ends of the channel. The model is essentially an extension of Shockley's original model to nonparallel gate junctions. Numerical results for several channel length-to-width ratios show slight deviations from Shockley's model in the terminal I–V characteristics for small length-to-width ratios but reduce to the results of Shockley's model for large length-to-width ratios. A significant feature of the model which differs from previous models is the absence of complete channel pinch-off in the current saturation region. The effect of carrier velocity saturation near the drain end of the channel is also discussed. For devices with small values of channel length-to-width ratio, carrier velocity saturation greatly reduces the saturation value of drain current. The importance of velocity saturation is found to depend upon a single parameter which is a function of the material constants and device dimensions.

Trapping of High Field Domain in n-Type GaAs

High field current-voltage characteristics of n-type GaAs were investigated in the temperature range of 200∼300°K with long samples, and below room temperature remarkable current saturation is found before the current oscillation begins. The critical field for current saturation was nearly the same as that for the Gunn effect at room temperature. The field distribution was observed with a traveling probe, and the formation of stationary high field domain was detected in the current saturation region. A mechanism is proposed to explain the trapping of the high field domain which results in the current saturation and hysteresis effect observed in this experiment.

Small signal properties of field effect devices

The small signal properties of field effect devices are treated analytically. The analysis is based upon an active, distributed transmission line analogy to the conductive channel of field effect devices. Within the limitations of the gradual channel approximation, a general analysis is presented which is applicable to both junction and MOS field effect devices. Equivalent circuits are obtained which describe field effect device characteristics in the region below saturation as well as in the current saturation region. Effects of parasitic elements on the terminal y parameters in practical devices are considered. Specific device models are considered for junction devices and MOS devices and the more important equivalent circuit parameters are evaluated in terms of the dc terminal voltages.

Large-Signal Transient Response of Junction Transistors

Transient response in the active region for junction transistors can be calculated from the conventional small-signal equivalent circuit. This small-signal characterization is adequate to calculate turn-on time and decay time. Carrier storage time, or time for the transistor operating point to move from the current saturation region to the active region, is calculated from a small-signal characterization of the transistor in the current saturation region. Frequency cutoff of alpha, ωN (radians/second) is the most important single transistor parameter affecting switching speed. It is possible with moderate driving current to switch the operating point from collector current cutoff to collector current saturation in times of the order of 3/ωN. To switch from collector current saturation to collector current cutoff, in times of the order of 3/ωN, carrier storage effects must be avoided.