Current-mode Signaling Scheme Research Articles

High-Speed On-Chip Signaling: Voltage or Current-Mode?

In this paper, we investigate several on-chip signaling schemes. Specifically, we compare different voltage-mode (VM) and current-mode (CM) signaling schemes considering power, performance, and robustness. In addition, we propose a new CM signaling scheme that uses a simple NAND-NOR gate transmitter circuit and a current-comparator-based receiver circuit. We implemented each signaling scheme using a 45 nm CMOS technology. The extracted simulation results show that a traditional CM signaling scheme consumes 58–78% less power compared to a traditional buffered VM signaling scheme in the 1–3 GHz frequency range. Our proposed CM signaling scheme consumes up to 95% and 81% lower power compared to buffered VM and existing CM schemes, respectively. In addition, the proposed CM signaling scheme has 37–41% lower latency with similar slew-rates compared to the buffered signaling scheme.

Modeling of CMS‐based nonuniform interconnects using FDTD technique

SummaryThis paper presents the finite‐difference time‐domain model of nonuniform interconnects including skin effect losses based on the current mode signaling (CMS). For accurate analysis, the nonlinear CMOS inverter is used as a driver for coupled nonuniform interconnects. These effects are incorporated in the proposed model using the modified alpha power law model. Additionally, high‐frequency losses are incorporated in the proposed model that further improves the accuracy. Using the proposed model, the performance of nonuniform interconnects is investigated using the CMS scheme. Time‐domain analysis model is derived from CMS nonuniform interconnects using finite‐difference time‐domain technique. Both inductive and capacitive couplings have been considered to incorporate coupling effects in interconnects. The efficiency of CMS interconnects is evaluated by comparing with conventional voltage mode signaling interconnects. The propagation delays and dynamic and functional cross talk effects at the far end of the coupled nonuniform interconnect are analyzed at the 32‐nm technology node. The proposed model results are validated using the standard HSPICE simulations.

Performance Comparison Between Current-Mode Signaling and Voltage-Mode Signaling for Single-Walled Carbon Nanotube Bundle Interconnects

Compared with the traditional copper material, carbon nanotube (CNT) has been identified as one of the most potential materials for interconnects in nanometer regime due to higher performance. However, for CNT interconnects, most of the researches focus on voltage-mode signaling (VMS) scheme, whereas current-mode signaling scheme (CMS) is meagerly investigated. The paper proposes an equivalent circuit model of two-line coupled single-walled CNT bundle interconnects, which is applicable to both CMS and VMS schemes. In addition, the model takes capacitive and inductive crosstalk into consideration. In CMS and VMS interconnects, the performance of victim line in the time domain is studied according to decoupling technique and ABCD parameter matrix approach at local, intermediate and global levels, respectively. The influence of aggressor line on victim line is discussed because of dynamic crosstalk and functional crosstalk. Furthermore, the paper comparatively analyzes the performance advantage between CMS interconnects and VMS interconnects. The results show that CMS interconnects have lower output voltage swing and propagation delay than VMS interconnects in the same condition. In terms of noise, CMS scheme has higher advantage for lesser noise peak, noise width and noise area. Moreover, it is found that the results obtained by ABCD parameter matrix approach have great consistency with Advanced Design System simulation results.

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.

This paper presents an IC implementation of on-chip learning neuromorphic autoencoder unit in a form of rate-based spiking neural network. With a current-mode signaling scheme embedded in a 500 × 500 6b SRAM-based memory, the proposed architecture achieves simultaneous processing of multiplications and accumulations. In addition, a transposable memory read for both forward and backward propagations and a virtual lookup table are also proposed to perform an unsupervised learning of restricted Boltzmann machine. The IC is fabricated using 28-nm CMOS process and is verified in a three-layer network of encoder-decoder pair for training and recovery of images with two-dimensional pixels. With a dataset of 50 digits, the IC shows a normalized root mean square error of 0.078. Measured energy efficiencies are 4.46 pJ per synaptic operation for inference and 19.26pJ per synaptic weight update for learning, respectively. The learning performance is also estimated by simulations if the proposed hardware architecture is extended to apply to a batch training of 60000 MNIST datasets.

The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits**Project supported by the Guangdong Provincial Natural Science Foundation of China (No. 2014A030313441), the Guangzhou Science and Technology Project (No. 201510010169), the Guangdong Province Science and Technology Project (No. 2016B090918071), and the National Natural Science Foundation of China (No. 61072028).

With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits. To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed. First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes. The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model. Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique and ABCD parameter matrix approach at local level, intermediate level and global level, respectively. Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits. It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.

A Novel Unified Model for Copper and MLGNR Interconnects Using Voltage- and Current-Mode Signaling Schemes

A novel unified model, for conventional copper and futuristic multilayer graphene nanoribbon (MLGNR) interconnects, based on a finite-difference time-domain (FDTD) technique has been proposed in this paper. The performance of quasi-transverse electromagnetic model of interconnects has been exhaustively analyzed for both voltage-mode signaling (VMS) and current-mode signaling (CMS) schemes. The effect of variations in edge roughness and dopant dependent Fermi energy in MLGNR interconnects has been examined. The crosstalk and coupling effects in interconnects have been investigated by incorporating capacitive and inductive interconnect parasitic elements. From the results carried out for 32-nm technology node, it has been observed that for similar dimensions and operating conditions, MLGNR interconnects show a significant performance improvement over the copper interconnects. The results also show that the CMS scheme outperforms VMS scheme at global wire lengths and is very suitable for state-of-the-art chip applications. The proposed model results are in close propinquity with the SPICE results. Furthermore, the FDTD-based model is computationally efficient compared to SPICE.

A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME

Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (CMS-Proposed) can acquire the same variation tolerance but consume less energy, compared with CMS-Bias with the original bias circuit (CMS-Original). Both the CMS schemes were fabricated in 180 nm CMOS technology. Simulation and measured results indicate that the two CMS interconnect circuits have the similar signal propagation delay when driving signal over a 10 mm line, but the CMS-Proposed offers about 9% reduction in energy/bit and 7.2% reduction in energy-delay-product (EDP) over the CMS-Original. Simulation results show that the two CMS schemes only change about 5% in delay when suffering intra-die variations, and have the same robustness against inter-die variations. Both simulation and measurements all show that the proposed bias circuits, employing self-biasing structure, contribute to robustness against supply variations to some extent. Jitter analysis presents the two CMS schemes have the same noise performance.