Current Mode Logic Research Articles

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Metal oxide semiconductor (MOS) current mode logic (MCML) is generally preferred for high-speed circuit design. In this paper, a novel low voltage folded (LVF) MCML D-Latch is designed. The existing topologies of the MCML D-Latch consume more power and operate at 1 V. The proposed D-Latch can operate at 0.6V with better delay and power management. MCML circuits minimize delay and perform fast operations, hence it can be used in high-frequency applications. The proposed LVF MCML D–Latch is analyzed with the parameters such as power, delay, power delay product and output noise using cadence virtuoso in 45 nm complementary metal oxide semiconductor (CMOS) technology at a voltage of 0.6 V and a temperature of 27 °C. The proposed technique achieves 62.11% of power reduction, transient response speed improved by 51.23% and noise cancellation becomes 26.13% improvement over the existing circuit. It also achieves 96% of output swing which is more efficient compared to others. Finally, the parametric analysis is performed with different temperatures to verify the stability of the proposed circuit. From the simulated results, it is clear that the proposed LVF MCML D-Latch provides better performance in high-speed phase locked loop (PLL) applications.

A 5.12-Gbps serializer circuit for front-end fast readout electronics of silicon pixelated detectors

Advanced synchrotron radiation sources are major facilities for analyzing the formation and evolution of material structure in multidisciplinary research, owing to their high luminosity, low emittance, wide energy bandwidth and other characteristics. In China, several advanced synchrotron radiation sources are under construction, including the HEPS (High Energy Photon Source) and SHINE (Shanghai high repetition rate X-ray Free Electron Laser and extreme light facility). These facilities are poised to become major multidisciplinary research platforms in China. To meet the requirements of pixel detectors in these facilities, dedicated pixel readout chips are being developed, including HEPS-BPIX and HYLITE. This paper presents a high-speed serializer circuit developed in a commercial 130-nm CMOS technology for the full-scale (128 × 128) pixel readout chip of HYLITE, which requires a data rate of 4 Gbps currently. The serializer consists of a 16-to-1 binary-tree multiplexer, a ring-oscillating-based phase-locked loop (RO-PLL) and a current-mode logic driving stage with a multi-stage pre-amplifier. Test results demonstrate its expected functionality within a wide operating range from 0.52 Gbps to 5.5 Gbps. At 5.12 Gbps, the measured jitter values are about 2 ps for random jitter, 20 ps for deterministic jitter, and 47 ps for total jitter with a 10−12 bit error rate. Additionally, the horizontal and vertical eye openings are 0.84 UI and 72%, respectively. These positive results indicate that the serializer meets the requirements of HYLITE.

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09%. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application.

K-band CMOS voltage-controlled oscillator using tail current modulation with half-output frequency

A CMOS voltage-controlled oscillator (VCO) using half-oscillation frequency signals as switched biasing is proposed to simultaneously improve the phase noise and DC-to-RF conversion efficiency. The effect of the flicker noise caused by the tail current source, which is the dominant factor of the VCO phase noise, can be reduced by the modulation using the half-frequency signals of the output. The conversion efficiency of the proposed VCO is improved by the leakage of the second harmonics of the modulation signal at the drain node of the current source, which is the same as the oscillation frequency of the VCO, thereby increasing the output power. The differential half-frequency signals are generated in the frequency divider, designed with the current-mode logic for minimizing the effect of parasitic components at high-frequency operation, which constitutes the frequency synthesizer without any additional circuits. The proposed VCO with the divider was fabricated on the size of 0.4 × 0.61 mm2 using a 65-nm CMOS process, including all pads. The measurement results showed a tuning range of 11.2% at the K-band and a phase noise of –109.86 dBc/Hz at the 1-MHz offset. The peak output power and DC-to-RF efficiency were measured to be 0.95 dBm and 16.64%, respectively, at the supply voltage of 1.2 V. A figure of merit of the proposed VCO was calculated to be –188.03 dBc/Hz.

High-performance LFSR circuit design based on XOR gates

The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

A Wideband and Low Reference Spur PLL with Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump and Symmetrical CML Divider

This paper presents the design and performance analysis of a wideband charge-pump phase-locked loop (CPPLL) characterized by low reference spur and low phase noise. The proposed CPPLL, operating as a wideband phase-locked loop (PLL) with a reference frequency of 100 MHz, achieves a wide tuning range of 40% from 2.0 GHz to 3.0 GHz. A clock feedthrough suppressed charge pump with additional bias current branches is used to reduce the PLL’s loop reference spur. The 4-stage current mode logic (CML) divide-by-2/3 circuit is utilized in the frequency divider to achieve high-speed frequency division. The circuit of an AND gate and latch in the 2/3 divider adopts a full differential symmetric structure to minimize the phase error of high-frequency differential signals. The voltage-controlled oscillator (VCO) is designed to provide a wide tuning range while optimizing the trade-off between the phase noise and power consumption. The fabricated PLL is implemented using a 0.13 µm CMOS process. Experimental measurements reveal a reference spur of −74.39 dBc at an oscillation frequency of 2.4 GHz. Moreover, the CPPLL achieves phase noise of −102.55 dBc/Hz@100 kHz and −127.15 dBc/Hz@1 MHz, while consuming 33.6 mW under a 1.2 V supply voltage. The integrated root-mean-square (rms) jitter, measured from 10 kHz to 10 MHz, is 340.99 fs, and the figure-of-merit (FoM) is −234.08 dB at a carrier frequency of 2.4 GHz, highlighting the potential of the proposed PLL for integrated circuit applications.

A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.

Asynchronous Sampling-Based Hybrid Equalizer

An equalizer architecture based on asynchronous sampling is described. The circuit implementation is a hybrid feed-forward equalizer (FFE) using three digital postcursor taps realized via level-crossing samplers (LCSs) and inverter-based delays. Utilizing a current mode logic (CML)-based summer stage, an analog main tap and digital postcursor taps are combined into an inductively tuned resistor load. With a 0.67-mV-rms simulated output-referred noise, the FFE has better noise performance than a conventional continuous-time linear equalizer (CTLE) and a slicer/latch-based decision feedback equalizer (DFE) circuit. Moreover, it exhibits very good linearity and group delay performance suitable for an equalizer. Using inverter-based delays enables area efficiency as well as the capability to tune the delay across process voltage and temperature (PVT) variations. Since the FFE is an event-driven combinational logic based on the incoming data, it does not require synchronous sampling coming from a high-speed clock and data recovery (CDR), and it is advantageous for high-speed and multirate operation as its power consumption scales with the data rate. Fabricated in 40-nm CMOS technology, the hybrid FFE achieves energy per bit of 2.7 pJ/bit with a 20-dB Nyquist insertion loss link at the 28.57-Gb/s nonreturn to zero (NRZ) data rate.

Simple and Accurate Model for the Propagation Delay in MCML Gates

In this article, we develop a simple and accurate model for evaluating the propagation delay in MOS Current-Mode Logic (MCML) gates. The model describes the behavior of MCML gates in a linear fashion despite the circuits themselves being non-linear. Indeed, we demonstrate that a linear model can be used, provided that, for each small-signal parameter, its average value calculated between the two different switching logic states is used. The proposed model is validated through simulations of MCML universal gates designed using modern nanometer processes. The model forecasts simulated values with an error lower than 4% and 20% in 65-nm standard CMOS and 28-nm Fully-Depleted Silicon-On-Insulator (FD-SOI), respectively.

Active loaded source-coupled logic: Applications and performance comparison

In this paper, we provide an extensive analysis of the newly introduced Active Loaded Source-Coupled Logic (ALSCL) family, which is a single-ended type of logic gate family with source-coupled circuit working principles. The proposed source-coupled logic family has analog-friendly behavior similar to previous source-coupled logic circuits, however, the proposed circuit structure has a simpler design methodology with high noise margins and robust characteristics to the device sizing, process variations, and temperature. Circuit design principles of the proposed ALSCL circuits are described, and performance analysis of various implementations is evaluated. The proposed logic circuit structure performance is tested using 0.18 µm technology with extensive simulations. The proposed logic family has simpler routing requirements compared to classical source-coupled circuits. The proposed circuit structure is functional without fine adjustment of the device sizing and the performance can be tuned by the bias current of the circuits, providing a wide range of performance characteristics with the trade-off for power consumption.

Design of fully differential fast SCL Schmitt-trigger delay element with tunable delay and hysteresis in design and run-time

Tuning the delay of the circuit during the circuit performance can give a chance to a circuit to reduce Process, Voltage and Temperature (PVT) effects on delay and frequency by resetting its delay in feedback. This paper presented a full differential Schmitt-trigger (ST) with tunable delay and hysteresis. The delay-hysteresis setting is done in the design phase by tuning the biasing current, sizing, bias voltage and also during the execute phase (run time) by a digital bit and restructuring the circuit and delay route. The presented ST can have high and low delays with different frequencies using a digital bit in the circuit. This can help the band selection for multi-band applications. A Flip Voltage Follower (FVF) circuit is used for the current tail to increase the current and increase the frequency bands. In this Schmitt-trigger delay changes associated with restructuring result in a 40 % power reduction. A circuit analysis for the equivalent circuit of the presented circuit has also been done and the factors affecting the frequency and delay change have been analyzed and investigated in the simulation. Monte Carlo and PVT analysis have also been performed for circuit accuracy. Power changing with an incremental delay in CMOS is improved and almost monotonous by designing Source-Coupled-Logic (SCL) Schmitt-trigger.

A Hybrid Transmitter With Voltage-Mode SST Preemphasis and Current-Mode Transmitter Equalization Capable of Operating at 77 K in DUNE

The Deep Underground Neutrino Experiment (DUNE) requires that the front-end transmitters operate at cryogenic temperature and drive 25–35 m long twin-axial (twinax) cables. To compensate the frequency-dependent channel loss over the long cables and alleviate the de-emphasizing of the low-frequency signal magnitude, a hybrid of a current-mode (CM) transmitter equalization (TXEQ) and a voltage-mode (VM) preemphasis is proposed. The TXEQ employs a finite-impulse response (FIR) filter to boost the high-frequency components while de-emphasizing the low-frequency signal magnitude, thereby flattening the overall channel frequency response and reducing the intersymbol interference (ISI). The VM preemphasis is proposed to further mitigate ISI by boosting the high-frequency portion without degrading the signal magnitude, allowing for high signal swing. The main driver utilizes VM source-series-terminated (SST) output stages, which offers higher signal swing and better power efficiency than the conventional CM logic (CML) drivers. To ensure the lifetime and reliability at cryogenic temperature, the transmitter is implemented in a 65-nm CMOS process operating at 1.1 V of supply voltage and employing transistors with larger than minimum lengths. Silicon measurement results at 77 K have validated the proposed approaches.

THE EYE OPENING IMPROVEMENT METHOD FOR A HIGH SPEED CURRENT MODE LOGIC DRIVER

A bandwidth improvement method of current mode logic (CML) drivers, of the integral circuit type specifically designed for high-speed serial data transmission systems is presented. These drivers are characterized by their ability to operate at high frequencies and their ability to provide a high level of signal integrity, which is critical for achieving high data rates and low error rates in high-speed systems. The key advantages of CML drivers such as providing a high level of signal integrity, the circuit topologies, operating modes, and performance characteristics are discussed. Furthermore, the challenges and limitations of CML drivers, as well as the recent advances in the field that enables the use of CML drivers in high-speed systems are also discussed. A driver constructed by the proposed method operating at 112 Gbps in PAM4 modulation consumes 9 mW under 0.9 V supply.

Analysis and design of current mode logic based on CNTFET

<abstract> <p>In this letter we present a current mode gate based on differential pair as an application of carbon nanotube field effect transistors (CNTFETs). The proposed circuit has two output logic gates: one is NAND, and the other is AND. To simplify the circuit realization we use all CNTFETs of the same type, all with the same lengths and carbon nanotube symmetry indices (n, m). Complex circuits could be obtained in current mode replicating the differential pair CNTFET along the current path. The proposed procedure allows simulation of transfer characteristics from voltage input to current output but also from voltage input to voltage output. Moreover, we can measure simulated power dissipation and delay times.</p> </abstract>

WITHDRAWN: DESIGN OF ADIABATIC CIRCUITS WITH REVERSIBLE LOGIC BASED FULL ADDER AND MULTIPLIER IN CURRENT-MODE LOGIC CIRCUITS FOR EFFICIENT POWER DISSIPATION

The widely used reversible full adder circuits are actualized in preceding research that optimizes design as well as speed of circuits.Theselogic gates that are reversible such as Peres, TSG, Toffoli, Feynman, and Fredkin are predominantly deployed in designing the reversible circuits. Nevertheless, its results are not promising in the context of dissipating static power. Power dissipation has turned out to be crucial issue in designing VLSI circuits. To overcome this problem, the energy recovery principle is introduced, and it is known as Adiabatic Logic. The famous adiabatic, low powered circuits work on reversible logic to store power and revert the same. Multiple Adiabatic Techniques (AT)is employed for dissipating the power in efficient manner. These ATs reduce power dissipation especially in VLSI circuits by performs both charging as well as discharging. The proposed research implements the Reversible Logic (RL) in Full Adder (FA) of Adiabatic Logic Reversible MOS Current-Mode Logic (MCML) FA generally termed Adiabatic Logic Reversible MCML Full Adder (FA) as well as on the Adiabatic Logic Reversible MCML multiplier. This is aimed to produce high speed circuits at reduced power. Reliable performance augmented with speedy operation is prominently exhibited in MCML than CMOS logic family. Coverage area along with improved power consumption may help in deployment of reversible logic in FA pertaining to MCML. Minimal quantity garbage output when given constant inputs is employed in reversible FA. The detailed experimental analysis portrays that proposed circuit can attain improved performance than existing RL like Feynman gate, Peres gate, TSG, Reversible MCML with Full Adder in the context of mean power, static power and current, and coverage area.

Neoteric Design Power Sustained 3-Bit Asynchronous Counter Using CNFET Based MCML Topology

Leading digital circuits namely register, flipflops, state machines and counters drive operational aspects and potential applications in Integrated Circuit (IC) industry. MOS Current Mode Logic (MCML) based implementations with rapid response and simultaneous generation of complemented output is all set to become indispensable in nano regime industry. This paper attempts to optimize and address performance-based analysis of digital circuits namely NAND, D flipflop and 3-bit asynchronous counter by practicing MCML based implementation. These circuits are contemplated on four design parameters namely delay (t_p), power (pwr), Power Delay Product (PDP) and Energy Delay Product (EDP). This research focuses on relative analysis and emanate a salient optimal application of Complementary Metal-Oxide-Semiconductor (CMOS) and Carbon Nanotube Field Effect Transistor (CNFET) based 3-bit asynchronous counter. In addition to this, the two configurations of the MCML counter are then compared against applied V_DD at 16-nm technology nodes using HSPICE simulator. CNFET based 3-bit MCML counter is observed to be much faster (9.75x), significant improvement in gross power dissipation (11.93x), material refinement in PDP and EDP (116.39x and 1165x) respectively as compared to the conventional counterpart. Therefore, CNFET based implementations comes to the fore as resilient technology supporting high level integration in nano scale regime.

A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic

Side-channel attack (SCA) is one of the physical attacks, which will reveal the confidential information from cryptographic circuits by statistically analyzing physical manifestations. Various circuit-level countermeasures have been proposed as fundamental solutions to eliminate the correlations between side-channel information and circuit’s internal operations. The existing solutions, however, will introduce nonnegligible power and area overheads, making them difficult to be deployed in resource-constrained applications. In this article, a novel three-independent-gate silicon nanowire field effect transistor (TIGFET) with the intrinsic SCA-resilience characteristics is introduced to balance the tradeoffs among cost, performance, and security of cryptographic implementations. We construct six TIGFET-based current mode logic (CML) gates that can retain lower power variation under all possible transitions compared to the CMOS counterparts. As a proof of concept, advanced encryption standard (AES), SM4 block cipher algorithm (SM4), and lightweight cryptographic algorithm PRESENT are implemented utilizing the TIGFET-based CML gates. Correlation power attack is performed to evaluate the improvement of SCA resilience. Simulation results verify that the TIGFET-based cryptographic implementations decrease 42.37% area usage, lower 61.16% energy efficiency, reduce <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.35\times $ </tex-math></inline-formula> power variation, and achieve a similar level of SCA resistance compared to the CMOS counterpart, which is applicable for the resource-constrained applications.

Characterization of a high bandwidth readout chain for the CMS phase-2 pixel upgrade

The CMS collaboration is building a new inner tracking pixel detector for the High-Luminosity LHC. Each pixel readout chip will be controlled with a single serial input stream at 160 Mb/s and will send out data via four current mode logic (CML) 1.28 Gb/s outputs. The readout chips will be grouped in modules and connected with up to 1.6 meters long low-mass electrical links to Low-Power Gigabit Transceivers (lpGBT) and Versatile Link PLUS Transceiver (VTRx+) modules that send the data optically to off-detector electronics at 10 Gb/s. The characterization of these components and system tests of the readout chain are presented.

A 13 Gbps 1:16 deserializer ASIC for NICA multi purpose detector project

This paper presents the design and test results of a 13 Gbps 1:16 deserializer ASIC fabricated in a 55 nm CMOS technology for Nuclotron-based Ion Collider fAcility (NICA) Multi Purpose Detector (MPD) project. The deserializer would be used in the downlink data transmission of MPD readout system to recover the serial data from the back-end to the parallel data for the front-end. The ASIC adopts a tree-type structure, consisting of a high-speed data receiver (RXDATA), a high-speed clock receiver (RXCLK), four levels of demultiplexer (DEMUX) modules, clock dividers and 16 Low-Voltage Differential Signaling (LVDS) drivers. The demultiplexer modules are composed of different numbers of high-speed DEMUX unit and low-speed DEMUX unit. The high-speed DEMUX unit and the high-frequency clock divider adopt an optimized compressed current mode logic (CML) differential structure to ensure the bandwidth with limited voltage headroom. The low-speed DEMUX unit and the low-frequency clock divider use CMOS latch to save power consumption. The duty cycle correction (DCC) circuit and the clock aligner are employed in the clock paths to ensure the correct duty cycle and aligned clock edges. In the chip test, the ASIC receives 13 Gbps serial data and outputs 16 channels of 812.5 Mbps data correctly with wide-open eye diagram. The tested power consumption is 203 mA with 1.2 V power supply including the RXDATA, the RXCLK and the 16 channels of LVDS drivers, and the core power consumption is 122.7 mA.

A transmitting circuit with adaptive calibration of output impedance for high speed interface

A transmitting circuit for high-speed interface is proposed in this paper. Optimized 10-bit parallel to serial conversion and embedded output impedance calibration are used for enhancing the performance of this transmitting circuit. Designed with 0.18 μm CMOS, this transmitting circuit can achieve an output data rate of 1.5625 Gbps with 10-bit 156.25 MHz parallel input. The output amplitude of the current mode logic (CML) driver is 1.28 Vpp with a jitter of 24.3 ps. After adaptive calibration, the mismatch between output impedance and its expected value is within 0.5%. The active area of this entire transmitting circuit is 220.1 μm × 197.5 μm. With 1.8 V power supply, the power consumption of this transmitting circuit is 41.2 mW at 1.5625 Gbps data rate.