Neoteric Design Power Sustained 3-Bit Asynchronous Counter Using CNFET Based MCML Topology

Abstract

Leading digital circuits namely register, flipflops, state machines and counters drive operational aspects and potential applications in Integrated Circuit (IC) industry. MOS Current Mode Logic (MCML) based implementations with rapid response and simultaneous generation of complemented output is all set to become indispensable in nano regime industry. This paper attempts to optimize and address performance-based analysis of digital circuits namely NAND, D flipflop and 3-bit asynchronous counter by practicing MCML based implementation. These circuits are contemplated on four design parameters namely delay (t_p), power (pwr), Power Delay Product (PDP) and Energy Delay Product (EDP). This research focuses on relative analysis and emanate a salient optimal application of Complementary Metal-Oxide-Semiconductor (CMOS) and Carbon Nanotube Field Effect Transistor (CNFET) based 3-bit asynchronous counter. In addition to this, the two configurations of the MCML counter are then compared against applied V_DD at 16-nm technology nodes using HSPICE simulator. CNFET based 3-bit MCML counter is observed to be much faster (9.75x), significant improvement in gross power dissipation (11.93x), material refinement in PDP and EDP (116.39x and 1165x) respectively as compared to the conventional counterpart. Therefore, CNFET based implementations comes to the fore as resilient technology supporting high level integration in nano scale regime.