Current Mismatch In Charge Pump Research Articles

A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

This paper presents a 5.7–6.0 GHz Phase-Locked Loop (PLL) design using a 130 nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (KVCO). With a reference frequency of 32.768 MHz, chip measurement results show that the frequency tuning range is 5.7–6.0 GHz, the reference spur is −68 dBc, the phase noise levels are −109 dBc/Hz and −135 dBc/Hz at 1 MHz and 10 MHz offset respectively for 5.835 GHz. Compared with existing designs in the literature, this work’s reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5 V supply voltage, the power dissipation with an output buffer of the PLL is 12 mW.

카운터 기반 디지털 보상 기법을 이용한 위상 고정 루프

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 ㎓ charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5㎂ current mismatch in CP. It was designed in a standard 0.13㎛ CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38㎽ with 1.5V power supply and effective area is 0.1804㎟.