Current Mirror Research Articles

Design and Optimization of a Highly Linear Power Amplifier with Novel Active Bias Circuit in InGaP/GaAs HBT MMIC Technology

This paper introduces a highly linear power amplifier (PA) that utilizes a 2-μm InGaP/GaAs hetero-junction bipolar transistor (HBT) process. As communication systems evolve in complexity, the demands for the linearity and static power consumption of HBT power amplifiers are becoming more stringent. Typically, there exists a trade-off relationship between linearity and static power consumption in the design process. Hence, this paper proposes a novel active bias circuit for HBT power amplifiers, along with its layout design. The proposed active bias circuit consists of a differential pair and a current mirror structure, designed to enhance PA linearity while maintaining low quiescent current. Additionally, a novel layout structure is implemented to achieve thermal coupling between the RF transistors and the active bias, further improving PA linearity. As a result of the implementation of the proposed active bias and layout structure, the PA demonstrates high linearity in both amplitude modulation to phase modulation (AM/PM) and amplitude modulation to amplitude modulation (AM/AM) performance, while simultaneously maintaining a low quiescent current. The three-stage PA prototype achieves notable performance metrics, including a peak gain of 32.6 dB at 5.6 GHz, gain flatness of ±0.5 dB from 5.15 GHz to 5.85 GHz, and P1dB of 32.1 dBm at a quiescent emitter current of 180 mA.

A 0.011%/V LS and −76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror

A 0.011%/V LS and −76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror

Quasi-floating gate MOSFET-based low power current mirror

Quasi-floating gate MOSFET-based low power current mirror

Low quiescent current LDO with FVF-based PSRR enhanced circuit for EEG recording wearable devices

This paper presents a low quiescent current low-dropout regulator (LDO) with an auxiliary amplifier, flipped voltage follower (FVF)-based power supply rejection ratio enhanced circuit (FBPEC) for electroencephalogram (EEG) recording devices. The FBPEC comprises a FVF filter, current mirror, and common-source amplifier. The FBPEC exploits the characteristics of FVF filter to reduce the current consumption and increase the gain at specific frequencies. The small-signal equivalent circuit reveals the dominant pole of the FBPEC, which is affected by the output impedance and load capacitance of the common-source amplifier. The proposed LDO is designed using a 0.18 μm CMOS process and has improved power supply rejection ratio (PSRR) up to 18 dB at frequencies above 10 kHz compared to the general LDO. The proposed LDO has a low no-load quiescent current 648 nA and a good figure-of-merit score compared to those of previous works, proving that the proposed circuit is an effective solution for use in wearable EEG recording devices.

Correction: A conceptual study on novel current mirror integrated cantilever (CMIC) mass sensor for micro-gram (µg) range sensing applications

Correction: A conceptual study on novel current mirror integrated cantilever (CMIC) mass sensor for micro-gram (µg) range sensing applications

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

Although Moore’s Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)…, longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor.

Design and simulation of a new current mirror circuit with low power consumption and high performance and output impedance

Design and simulation of a new current mirror circuit with low power consumption and high performance and output impedance

Analysis of a Low-Power OTA-Based Neural Amplifier Design for EEG Signal Acquisition

This paper presents the design of an efficient operational transconductance amplifier (OTA) to be explicitly used for electroencephalogram (EEG) signal acquisition in neural amplifiers (NAs). The central objective of this study revolves around addressing the fundamental compromise between noise and power in the design of NAs. The overarching goal is to effectively mitigate this trade-off by introducing novel approaches. The proposed design’s novelty lies in utilizing an adaptive biasing technique instead of the traditional current mirror biasing technique. Furthermore, the conventional input differential pair of the OTA is modified to employ a self cascode flipped voltage follower (SCFVF), which eventually reduces power consumption of the NA to 0.822 [Formula: see text]W. Additionally, notable improvements in noise performance are achieved and found to be 624.9 nV/[Formula: see text] at 1 Hz. The gain and bandwidth range of the input low-noise amplifier is 54.2 dB and 2.8 Hz–207 Hz, respectively, which effectively amplifies low-amplitude noisy incoming signals, addressing the specific requirements of EEG signal acquisition.

Photovoltaic hotspots: A mitigation technique and its thermal cycle

In the rapidly evolving field of solar energy, Photovoltaic (PV) manufacturers are constantly challenged by the degradation of PV modules due to localized overheating, commonly known as hotspots. This issue not only reduce the efficiency of solar panels but, in severe cases, can lead to irreversible damage, malfunctioning, and even fire hazards. Addressing this critical challenge, our research introduces an innovative electronic device designed to effectively mitigate PV hotspots. This pioneering solution consists of a novel combination of a current comparator and a current mirror circuit. These components are uniquely integrated with an automatic switching mechanism, notably eliminating the need for traditional bypass diodes. We rigorously tested and validated this device on PV modules exhibiting both adjacent and non-adjacent hotspots. Our findings are groundbreaking: the hotspot temperatures were significantly reduced from a dangerous 55 °C to a safer 35 °C. Moreover, this intervention remarkably enhanced the output power of the modules by up to 5.3%. This research not only contributes a practical solution to a longstanding problem in solar panel efficiency but also opens new pathways for enhancing the safety and longevity of solar PV systems.

A conceptual study on novel current mirror integrated cantilever (CMIC) mass sensor for micro-gram ($$\mu$$g) range sensing applications

A conceptual study on novel current mirror integrated cantilever (CMIC) mass sensor for micro-gram ($$\mu$$g) range sensing applications

Design of BJT-JFET Operational Amplifiers on the Master Slice Array

The use of dual-gate field-effect transistors located on the base matrix crystal MH2XA031, controlled by a p–n junction needed to reduce the input current of operational amplifiers is studied. Typical circuits of operational amplifiers, containing: source repeaters connected to the inputs of the operational amplifier on complementary bipolar transistors; input differential stage on p-JFET with a “current mirror” load on n–p–n-transistors; input differential in the form of a “folded cascode” on a p-JFET are analyzed. To minimize the input current, it is re commended to use bootstrapped feedback to keep the drain-to-source voltage of the input JFETs low, independent of the input common-mode voltage, and to connect only the top gate of the dual-gate JFET to the op-amp input. The electrical circuits for MH2XA031 elements and the results of circuit simulation of the developed amplifiers, called OAmp10J, OAmp11.1, OAmp11.2, are presented. Accounting the established features of the input stages and operating modes of active elements in circuit design will allow to create an operational amplifier with the required combination of basic parameters.

The Conjugated Current Mirrors: A General Enhancement in Transconductance Amplifiers

The Conjugated Current Mirrors: A General Enhancement in Transconductance Amplifiers

Bulk Cum QFG-Driven FVF Double Recycling Current Mirror Subthreshold OTA Based CCII+ Cell and Applications

This paper presents a low-voltage low-power second generation CCII+ cell using bulk-driven FVF class AB mode operated double recycling current mirror OTA. The OTA is used in the input core of CCII+ cell utilizes bulkcum Quasi Floating Gate (QFG)-based voltage to current converter and Partial Positive Feedback (PPF) to enhance the performance of the circuit. The circuit permits closely railto- rail input common mode range, high output current drive capability with low dual power supply of ± 0.25 V. This circuit produces low input referred noise of 1.65 μV/sqrt Hz, dissipates ultra-low power of 342 nW and is suitable for lowfrequency applications, such as bio-signal processing. Further, to validate this design, a MISO type voltage mode biquadratic filter and voltage mode two phase quadrature oscillator are currently being implemented using this CCII+ cells. The circuit is simulated in tanner EDA tools using 180 nm n-tub CMOS process technology with low bias current of 18 nA.

8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation

8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation

Analysis and Design of MBCFET and Their Circuit Application in Current Mirror and DRAM

This research paper addresses the challenges associated with transistor downscaling, particularly short channel effects (SCEs) in conventional silicon metal-oxide-semiconductor field-effect transistors (Si MOSFETs), and introduces Multi-Bridge-Channel MOSFETs (MBCFETs) as a potential solution. This study explores their attributes, emphasizing flexibility and faster switching, and comprehensively examines device parameters, fabrication processes, and simulation frameworks, offering a detailed analysis of critical factors influencing MBCFET performance. Investigating the intricate relationship between nanosheet dimensions and device characteristics, the research provides insights for optimized design and integration into future semiconductor technologies. The research looks at how the gate electrode's work function, the nanosheets' thickness and count, and the different types of doping affect important device properties such as transconductance, drive current, OFF-state current, and threshold voltage. Furthermore, the study is being carried out to form a current mirror and DRAM circuit by using the proposed MBCFET. This study demonstrates the transformative potential of MBCFETs in high-performance electronic applications.

Low voltage high bandwidth FVF current mirror using quasi floating self-cascode output stage

Low voltage high bandwidth FVF current mirror using quasi floating self-cascode output stage

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.

Evolutionary Optimization Techniques in Analog Integrated Circuit Designs

The proposed genetic algorithm (GA) and particle swarm optimization (PSO) applied for the optimal design of a one-stage operational amplifier circuit with a current mirror load are studied in this work. The sizes of transistors are optimized using the proposed GA and PSO for improved areas and performance parameters of the circuit. A number of performance parameters are collected from the data set created by GA and PSO to optimize the size of transistors and other design parameters. The Spectre simulator is chosen for the simulation of circuit parameters to obtain necessary for the GA and PSO algorithm. Post-optimization results justify that the proposed GA and PSO methods are competitive with differential evolution regarding convergence speed, design specifications, and the optimal CMOS one-stage operational amplifier circuit parameters.

A 28 nm CMOS low-noise amplifier with novel redundant noise cancellation technique beyond ultra-wideband for 6G-based wireless systems

In the current scenario, almost 5G-based wireless systems have been deployed everywhere but still performance trade-offs of RF amplifiers in the sub-nanometer regime are challenging. In this work, a high-performance low-noise amplifier (LNA) is realized in a 28 nm CMOS process with a novel redundant noise cancellation technique (RnC). The proposed technique improves the noise figure (NF) beyond the ultra-wideband of a low-noise amplifier (LNA) and minimizes the trade-off in the 28 nm process. An ultra-low NF is achieved in two approaches; Firstly, a current mirror network is employed in the primary path to cancel the thermal noise of the dominant transistor of a common gate-common source (CG-CS) without an extra power supply. Secondly, an auxiliary amplifier stage is introduced here to reduce the noise which contributes to the current mirror circuit and cancels the distortion in CG-CS topology without violating the traditional noise cancellation condition. In addition, an analytical approach is followed to optimize the input impedance, gain bandwidth and noise figure. Hence, the proposed RnC LNA benefits in achieving good tradeoffs among gain, bandwidth, NF, and power consumption in 28 nm technology node. The proposed RnC LNA is analyzed and fabricated using CMOS 28 nm technology, occupying an area of 0.011 mm2. The proposed design achieves an optimum performance: nearly flat gain of 15.3 dB, minimum NF of 1.7 dB over 1.7 to 12.52 GHz, and an IIP3 of − 2.6 dBm at 6.5 GHz. The proposed LNA consumes ultra-low power consumption of 1.8 mW under the power supply of 1 V.

Improving noise levels based on amplifier structure analysis

As the core component of electronic circuits, amplifiers play a pivotal role in fields such as communications, medical care, audio processing, instrumentation, scientific research and military technology. However, the noise problem of the amplifier has a direct impact on the reliability and accuracy of the system, how to reduce the impact of noise is crucial. This paper aims to study and solve noise problems in amplifier design. The first part focuses on the design of operational amplifiers. By adjusting the circuit structure and introducing current mirrors, the noise of the input and output stages is successfully reduced and the amplifier performance is improved. The second part focuses on the design of instrumentation amplifiers, introducing kT/C noise elimination technology, chopper modulation structure solves the noise and aliasing problems in switched capacitor instrumentation amplifiers and improve performance.