Current Kink Research Articles

Current Kink Effect in β-Ga₂O₃ MOSFETs Induced by Incomplete Ionization of Donors

Current Kink Effect in <i>β</i>-Ga₂O₃ MOSFETs Induced by Incomplete Ionization of Donors

A Lumped-Parameter Equivalent Circuit Model for Perovskite Solar Cells’ S-Shaped I-V Kinks

A lumped-parameter circuit model is proposed to describe the S-shaped I-V characteristics with current kinks exhibited in perovskite solar cells (PSCs). The physics-based model represents the electrical effect of the electrode contact interface. A Difference-Microvariation (DM) principle is used to derive the explicit solution of the model, which gives accurate and efficient descriptions for the current kinks of PSCs in a single-piece formula. The good agreement between our proposed model and numerical iteration results or reconstructed experimental data proves its validity. We believe that, the improved model can provide optimization direction for device process. Meanwhile, the proposed DM principle can perform as an efficient and serviceable tool to implement the lumped-parameter model compactly into TCAD simulators of PSCs.

Analyzing S-Shaped I–V characteristics of solar cells by solving three-diode lumped-parameter equivalent circuit model explicitly

In order to analyze and optimize new generation solar cells’ electrostatic performances, lumped-parameter equivalent circuit model is a common method to simulate S-shaped I–V characteristics including linear, exponential, or exponential-like current kinks. Unfortunately, three-diode lumped-parameter model is still inevitable to be solved generally in numerical iteration method. The absence of explicit solution to three-diode lumped-parameter model is actually the main bottleneck of implementing the model into photovoltaic device and circuit simulators in compact. In this paper, to overcome the problem of three-diode model’s implementation into simulators, we proposed an explicit solution to the model based on the regional approach, where high accuracy and low computation time cost are the main features of such a solution. Analytical derivation and correction for the solution to transcendent I–V equation in three-diode model leads to high computation accuracy, and avoidance of numerical iteration methods introduces low computation time cost. Finally, numerical iteration results and reconstructed experimental data of solar cells are used to validate the accuracy and applicability of our proposed explicit solution. As a result, high accuracy and efficiency of the explicit solution make it possible to implement three-diode lumped-parameter equivalent circuit model into photovoltaic device and circuit simulators and explain I–V characteristics of new generation solar cells.

Improved linearity, stability, and thermal performance of multi-mesa-channel AlGaN/GaN HEMTs

AlGaN/GaN high-electron-mobility-transistors (HEMTs) are expected to revolutionize the power-switching technology owing to excellent intrinsic material properties of GaN, which include wide bandgap, high carrier saturation velocity, large critical electric field, and good thermal conductivity. However, the widespread deployment of these devices is still hounded by stability issues such as current collapse, kink effect, transconductance collapse, and self-heating. To address these issues, we developed the multi-mesa-channel (MMC) HEMT, in which a periodic trench structure is fabricated only under the gate electrode. The formation of the periodic trench results into parallel nanowire channels with 2-D electron gas (2DEG) surrounded by the gate electrode. A surrounding-field effect in the MMC structure results in a shallower threshold voltage, thus giving another degree of freedom for obtaining enhancement mode operation. In this work, we would present experimental results that demonstrate the superior performance of MMC AlGaN/GaN HEMTs over their conventional planar counterparts. On top of being less vulnerable to current collapse, MMC devices also exhibit improved linearity, stability, and thermal performance, which are all positive attributes required for optimum device operation.

RF Performance of a Highly Linear Power Amplifier EDNMOS Transistor on Trap-Rich SOI

Results specific to power amplifiers (PAs) designed using a SOI EDNMOS transistor free of kinks in ID-VD plane and high breakdown voltage are presented. The suppression of the drain current kink and improvement in breakdown voltage are achieved by the omission of the N+ source implant step. Instead, the source junction is realized by an optimized NLDD implant step only, allowing the formation of an under-source body contact. This approach is highly suitable for integration with RF switch and low-noise amplifiers on the same thin film SOI substrate. The improved channel conductance is found to give rise to highly linear amplitude and phase characteristics under high power conditions when the optimized EDNMOS device is used standalone as a PA.

Current Kink and Capacitance Frequency Dispersion in Silicon PIN Photodiodes

Silicon PIN photodiodes in the visible wavelength range have been widely applied in aerospace, defense, security, medical, and scientific instruments because of their high sensitivity and low cost. In this paper, the phenomena of the current kink and the capacitance frequency dispersion are observed. Contamination at the p-type Ohmic contact interface is proposed to explain the current kink effect and capacitance frequency dispersion, according to the temperature-dependent I-V measurement results in which trap-assisted tunneling process demonstrated.

Crowdsourcing yields a new standard for kinks in protein helices.

Kinks are functionally important structural features found in the α-helices of proteins. Structurally, they are points at which a helix abruptly changes direction. Current kink definition and identification methods often disagree with one another. Here we describe a crowdsourcing approach to obtain a reliable gold standard set of kinks. Using an online interface, we collected more than 10,000 classifications of 300 helices into straight, curved, or kinked categories. We found that participants were better at discriminating between straight and not-straight helices than between kinked and curved helices. Surprisingly, more obvious kinks were not necessarily identified as more localized within the helix. We present a set of 252 helices where more than 50% of the participants agree on a classification. This set can be used as a reliable gold standard to develop, train, and compare computational methods. An interactive visualization of the results is available online at http://opig.stats.ox.ac.uk/webapps/ahah/php/experiment_results.php .

P‐9: Bridged Grain MIC Poly‐Si Thin‐Film Transistors with Sputtered AlOx as Gate Dielectrics

AbstractBridged grain (BG) technology was applied to fabricate MIC poly‐Si TFTs with AlOx gate dielectrics. The threshold voltage (Vth) and subthreshold swing (SS) of MIC TFTs are greatly improved. Meanwhile, the drawback of using high‐k dielectrics, such as large off‐state leakage current and early kink effect was effectively suppressed by using BG structure. Combination of BG and high‐k gate insulators makes the resulting device a promising candidate for system on panel applications.

Compact modeling of 0.35 μm SOI CMOS technology node for 4 K DC operation using Verilog-A

Compact modeling of MOSFETs from a 0.35 μm SOI technology node operating at 4 K is presented. The Verilog-A language is used to modify device equations for BSIM models and more accurately reproduce measured DC behavior, which is not possible with the standard BSIM model set. The model presented exhibits convergent behavior and is shown to be experimentally accurate at 4 K. No design tool currently in place exhibits convergence and/or accuracy over this range. The Verilog-A approach also allows the embedding of nonlinear length, width and bias effects into BSIM calculated curves beyond those that can be achieved by the use of different BSIM parameter sets. Nonlinear dependences are necessary to capture effects particular to 4 K behavior, such as current kinks. The 4 K DC behavior is reproduced well by the compact model and the model seamlessly evolves during simulation of circuits and systems as the simulator encounters SOI MOSFETs with different lengths and widths. The incorporation of various length/width and bias dependent effects into one Verilog-A/BSIM4 library, therefore, produces one model for all sets of devices called up in a given product design kit (PDK) for this technology node.

Evaluation and Resolution for Nonideal Characteristics of Complementary Metal–Oxide–Semiconductor Devices Fabricated on Silicon-on-Insulator

By virtue of inherent advantages including higher controllability of gate over channel electrons, very low junction capacitance, and soft-error immunity of silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs), there have been increasing demands for implementation of devices on SOI. Operating the systems constructed on SOI calls for more accurate and tangible understanding of complementary MOS (CMOS) devices on SOI. From this motivation, we fabricated both n- and p-type MOSFETs of various dimensions, operated them under different bias conditions, and characterized them in various aspects in this work. Furthermore, we did our utmost to quantify nonideal characteristics such as drain current kink and double humps of large-scale n/p-MOSFETs on SOI. Although the devices in logic or memory arrays are miniaturized to sub-100 nm nowadays, large-scale devices can still be used for specific purposes such as peripheral circuits of memory arrays. Therefore, we examine long-channel devices to clearly determine what matters in the operation. These experiments may provide us guidelines in the diverse SOI CMOS processes.

An Investigation of Negative Differential Resistance and Novel Collector–Current Kink Effects in SiGe HBTs Operating at Cryogenic Temperatures

In this paper, a new negative-differential-resistance (NDR) effect and a novel collector-current kink effect are investigated in the cryogenically operated SiGe heterojunction bipolar transistors (HBTs). Theory based on an enhanced positive-feedback mechanism associated with heterojunction barrier effect at deep cryogenic temperatures is proposed to explain both the observed NDR and the collector-current kink. The accumulated charge induced by the barrier effect acts at low temperatures to enhance the total collector-current, indirectly producing both phenomena. This theory is confirmed using the calibrated 2-D DESSIS simulations over temperature. These unique cryogenic effects also have significant impact on the ac performance of SiGe HBTs operating at high injection. Technology evolution plays an important role in determining the magnitude of the observed phenomena, and the scaling implications are addressed. In addition, the present NDR effect is also compared with previously reported NDR and hysteresis effects observed in highly scaled SiGe HBTs operating under forced-I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> -base bias. The input drive condition of the transistor during its use in circuits, either under pure forced-current bias or under pure forced-voltage bias, or more practically, somewhere in between, determines the magnitude of the observed NDR and is of potential concern for circuit designers and must be carefully modeled

Influence of the extrinsic base on the base current kink in SiGe BJTs

A new explanation for the abrupt increase of the base current in SiGe BJTs is proposed. It is suggested that the electron current flowing laterally along the extended base is responsible for this abrupt change. The magnitude of this effect is controlled by the location of the extrinsic base region relative to the emitter and intrinsic base regions.

Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model

A four-terminal physical subcircuit model for floating body (FB) partially depleted (PD) and near fully depleted ( near FD) SOI CMOS devices is presented. The model accounts for the unique characteristics of PD devices associated with the drain ( V ds) induced floating body effects. Unlike other models, the proposed circuit model accounts physically for the back MOSFET device, and accurately predicts the bias dependence of the current kink in near FD devices. It allows for proper capacitance scaling and more accurate simulations related to the front and back oxides/channels. Self-heating effects related to the low thermal conductivity of the back oxide are also included. The circuit model is SPICE compatible and provides insights for understanding optimal device design needs for high performance. A simple technique for extracting the model parameters is described. The model is verified by the good agreement of the simulation results with the experimental data. The predictive capabilities of the subcircuit model are supported by circuit level simulation examples.

Impact of CMOS processing steps on the drain current kink of NMOSFETs at liquid helium temperature

The impact of certain CMOS processing steps on the drain current kink in nMOSFETs fabricated in a 0.7-/spl mu/m technology and operated at liquid helium temperatures (LHTs) is investigated, The kink is successfully suppressed when implementing a lightly-doped drain (LDD) or a p-well, while the application of a threshold voltage adjust implantation has a more subtle effect. In order to understand the observations in more detail the impact ionization rate in the different splits is analyzed, whereby particular efforts are spent to accurately determine the saturation drain voltage V/sub DSAT/ from the 4.2 K output characteristics. An optimized method based on the extrapolation of the output resistance yields consistent data and a critical field for inversion layer velocity saturation of (1.2/spl plusmn/0.1)/spl times/10/sup 4/ V/cm at 4.2 K. It is finally demonstrated that a high-energy room-temperature proton irradiation has a qualitatively similar beneficial effect on the kink as the use of an LDD, for example.

Ideal Current Layers and Kink Instability in Line-Tied Coronal Loops

The development of the kink instability in line-tied coronal loops is studied using a cylindrical MHD code. When the twist of magnetic field lines of the initial configuration exceeds a critical value, an ideal kink mode develops and drives this unstable equilibrium towards a secondary bifurcated equilibrium containing an electric current concentration. Contrary to a periodic untied configuration where a current sheet is ideally generated, the current layer is non-singular with a non-zero thickness and a finite amplitude. This current concentration extends along all the loop length and takes the form of an helical ribbon of intense current. The numerical results give an algebraic linear-like scaling of the characteristics of the current layer (amplitude and thickness) as a function of the aspect ratio of the loop. An interpretation in terms of axial field-line bending of the three-dimensional kinked equilibrium is proposed.

Compact non-local modeling of impact ionization in SOI MOSFETs for optimal CMOS device/circuit design

A comprehensive but compact non-local model for impact ionization current in scaled SOI MOSFETs is developed. The model, applicable to both fully depleted and non-fully depleted SOI CMOS, is intended for device/circuit simulation and has been implemented as post-processing in a circuit simulator SOISPICE [J. G. Fossum, SOI-SPICE-4 ( FD/SOI and NFD/SOI MOSFET Models). University of Florida, Gainesville, FL (March 1995)]. The model is based on transforming the empirical field-dependent impact ionization rate into a carrier temperature-dependent one via a quasi-steady-state approximation of the energy balance equation. The model is valid for weak as well as strong inversion. It is verified via predictions of structure-dependent drain-source breakdown and current kinks in a variety of floating-body SOI MOSFETs. SOISPICE simulations reveal insight into the design optimization of scaled SOI CMOS devices and circuits in which the breakdown, due to the parasitic BJT driven by impact ionization, must be controlled.

Transient behavior of the kink effect in partially-depleted SOI MOSFET's

The behavior of transients in the drain current of partially-depleted (PD) SOI MOSFET's down to L/sub eff/=0.2 /spl mu/m is examined as a function of drain bias, gate pulses of varying magnitude (V/sub GS/), pulse duration, and pulse frequency. At fixed V/sub DS/, the gate is pulsed to values ranging from 0.1 V above V/sub T/ to V/sub GS/=V/sub DS/. A slow transient is seen when the drain is biased at a V/sub DS/ where the current kink is observable. This slow transient can be on the order of microseconds depending on the relative magnitude of the impact ionization rate. For short times after the pulse edge or for very short pulses at low frequencies, it is shown that the subthreshold drain current value can be very different from the corresponding DC, and that the kink characteristic of PD MOSFET's disappears. However, the kink values can be approached when the pulse frequency and/or duration applied to the gate is increased, due to the latent charge maintained in the floating body at higher frequencies. No transient current effects were observed in fully-depleted SOI MOSFET's. >

Modeling for floating body effects in fully depleted SOI MOSFETs

A model based on SOI MOSFET and BJT device theories is developed to describe the current kink and breakdown phenomena in thin-film SOI MOSFET drain-source current-voltage characteristics operated in strong inversion. The modulation of MOSFET current by raised floating body potential is discussed to provide an insight for understanding the suppression of current kink in fully depleted thin-film SOI devices. The proposed analytical model successfully simulates the drain current-voltage characteristics of thin-film SOI n-MOSFETs fabricated on SIMOX wafers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

CMOS operational amplifier performance at cryogenic temperatures

The performance of three different two-stage CMOS operational amplifiers (op-amps) at temperatures below 100 K was investigated. The open-loop gain and unity-gain frequency increased by at least a factor of 2 and 1.3, respectively, when cooled from room temperature to 50 K. However, because of current kinks in the n-channel output transistors, all of the op-amps developed severe non-linearities in their output characteristics at temperatures below 50 K with ±5 V supplies. Reducing the supply voltages extended the op-amps useful cold temperature operating range. One op-amp was found to operate quite well down to 30 K with the supplies reduced to ±2.5 V. Methods of improving the cold temperature operation of CMOS op-amps are discussed.

N-channel accumulation layer MOSFET operating at 4 K

An accumulation layer n-channel MOSFET that operates at 4 K has been fabricated. Sharp hysteretic current kinks in the I– V characteristic are observed, where the transistor switches discontinuously between two well defined states. The kinks are modelled in terms of changes in the device potential configuration due to holes generated by avalanche breakdown in the high electric field region near pinch off. Noise measurements which elucidate the physical mechanisms causing the current kinks are presented.