Evaluation and Resolution for Nonideal Characteristics of Complementary Metal–Oxide–Semiconductor Devices Fabricated on Silicon-on-Insulator

Abstract

By virtue of inherent advantages including higher controllability of gate over channel electrons, very low junction capacitance, and soft-error immunity of silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs), there have been increasing demands for implementation of devices on SOI. Operating the systems constructed on SOI calls for more accurate and tangible understanding of complementary MOS (CMOS) devices on SOI. From this motivation, we fabricated both n- and p-type MOSFETs of various dimensions, operated them under different bias conditions, and characterized them in various aspects in this work. Furthermore, we did our utmost to quantify nonideal characteristics such as drain current kink and double humps of large-scale n/p-MOSFETs on SOI. Although the devices in logic or memory arrays are miniaturized to sub-100 nm nowadays, large-scale devices can still be used for specific purposes such as peripheral circuits of memory arrays. Therefore, we examine long-channel devices to clearly determine what matters in the operation. These experiments may provide us guidelines in the diverse SOI CMOS processes.