Current Id Research Articles

Mechanism of Hump Phenomenon in the I-V Characteristics of Amorphous in-Ga-Zn-O Thin Film Transistors Under Positive Bias and Illumination Stress

Amorphous indium-gallium-zinc-oxide (a-IGZO) has been considered as attractive material, because it has high electron mobility, good uniformity, high on/off ratio, and low processing temperature. Despite their promising features, a-IGZO TFTs are unreliable under gate-bias stress and illumination stress. In particular, under positive bias temperature stress (PBTS), a-IGZO TFTs have threshold voltage shift because of electron trapping at the gate insulator (GI) or interface between GI layer and a-IGZO layer. Another reliability problem under PBTS is a hump that occurs in the subthreshold regime of the I-V characteristics. Mechanism of the hump under PBTS has been studied consistently; however, effects of illumination to hump phenomenon was not considered. In real applications, TFTs are inevitably exposed to visible light emitted from the backplane unit in AMLCD panels or the self-emitting diode in OLED panels. Therefore the effects of positive bias illumination temperature stress (PBITS) to the hump phenomenon on a-IGZO TFTs have to be understood to solve reliability problem. Back channel etch (BCE) structure a-IGZO TFTs were subjected to PBTS and PBITS. A gate voltage stress VGS of 40 V was applied to the gate electrode while drain and source electrodes were grounded. Temperature was 90 ℃. Intensity of White LED was 5000 lux. The stress was interrupted periodically to measure the I-V characteristics of TFTs. During measurements, gate voltage VGS was swept from -20 to 20 V, keeping the drain voltage VDS at 0.1 V. We defined two kinds of threshold voltages : (1) On-current threshold voltage VON (VGS at which drain current ID is 100 nA), and (2) Hump threshold voltage VH (VGS at which drain current ID is 1 nA) (Fig. 1). Threshold voltage is more positively shifted under PBTS than under PBITS, however in terms of the hump, degradation of a-IGZO TFTs is more serious under PBITS than under PBTS; after the hump was induced, VH is shifted more negatively under PBITS than under PBTS. When VH is shifted more negatively, high negative gate bias should be applied to off the TFTs. I-V characteristics shifted positively at the early stage of stress time. After hump was induced, however, I-V characteristics had bidirectional shift (Fig. 1); VON shifted positively and VH shifted negatively. VON shifted more positively under PBTS than under PBITS, while VH shifted more negatively under PBITS than PBTS (△VH under PBTS = 0.74 V and △VH under PBITS = 1.88 V, from 4000 s to 10000 s) (Fig. 2). To investigate effects of illumination in detail, a-IGZO TFTs under PBITS with different wavelength illumination was measured. VON shifted more positively under red illumination than under blue illumination, while VH shifted more negatively under blue illumination than under red illumination (△VH under PBITS with red illumination = 0.76 V and △VH under PBITS with blue illumination = 2.55 V, from 4000 s to 10000 s) (Fig. 3). This means that VH was affected by the illumination with short wavelength lights. In this work, I-V characteristics of a-IGZO TFTs was measured to quantify the mechanism that causes the hump in the I-V curve of a-IGZO TFTs under PBTS and PBITS. We focused on finding hump phenomenon in terms of illumination effects that have remained unclear. We will explain the effects of illumination to hump phenomenon, and difference between mechanism of the hump under PBTS and PBITS. Through this study, we could broaden our knowledge about the effect of illumination on a-IGZO TFT. Figure 1

Top-Down Nanofabrication and Characterization of 20 nm Silicon Nanowires for Biosensing Applications.

A top-down nanofabrication approach is used to develop silicon nanowires from silicon-on-insulator (SOI) wafers and involves direct-write electron beam lithography (EBL), inductively coupled plasma-reactive ion etching (ICP-RIE) and a size reduction process. To achieve nanometer scale size, the crucial factors contributing to the EBL and size reduction processes are highlighted. The resulting silicon nanowires, which are 20 nm in width and 30 nm in height (with a triangular shape) and have a straight structure over the length of 400 μm, are fabricated precisely at the designed location on the device. The device is applied in biomolecule detection based on the changes in drain current (Ids), electrical resistance and conductance of the silicon nanowires upon hybridization to complementary target deoxyribonucleic acid (DNA). In this context, the scaled-down device exhibited superior performances in terms of good specificity and high sensitivity, with a limit of detection (LOD) of 10 fM, enables for efficient label-free, direct and higher-accuracy DNA molecules detection. Thus, this silicon nanowire can be used as an improved transducer and serves as novel biosensor for future biomedical diagnostic applications.

Load compensation based on frame considering low-order dominant harmonics and distorted power system

In this paper, by considering voltage distortion and frequency variation, the control strategy of synchronous reference frame (SRF) for three-phase shunt active power filter has been improved. In the SRF compensation method a conventional low pass filter (CLPF) is used to extract the dc component of the d-axis current (Id). Unfortunately in the presence of low-order harmonics of the load current (second and third ones), the transient response time is increased. If the amplitude of these harmonics are high, the distortions in CLPF output signal are increased, and as a result, the desired compensation cannot be achieved. In this paper to overcome this problem, a novel numerical LPF is designed and implemented based on variable forgetting factor-recursive least squares (VFF-RLS). The advantages of the proposed filter over CLPFs include independence of the load current harmonic components, fast dynamic and high accuracy of the response. Moreover, due to the malfunction of the conventional phase locked loop (PLL) in polluted and variable frequency environment, a second order generation integrator-frequency locked loop (SOGI-FLL) based on fuzzy logic controller (FLC) and wavelet transform (WT) is proposed. Effectiveness of the proposed method is evaluated with both simulations and experimental results in a three-phase power system.

Metal electrode dependent field effect transistors made of lanthanide ion-doped DNA crystals

We fabricated lanthanide ion (Ln3+, e.g. Dy3+, Er3+, Eu3+, and Gd3+)-doped self-assembled double-crossover (DX) DNA crystals grown on the surface of field effect transistors (FETs) containing either a Cr, Au, or Ni electrode. Here we demonstrate the metal electrode dependent FET characteristics as a function of various Ln3+. The drain–source current (Ids), controlled by the drain–source voltage (Vds) of Ln3+-doped DX DNA crystals with a Cr electrode on an FET, changed significantly under various gate voltages (Vg) due to the relative closeness of the work function of Cr to the energy band gap of Ln3+-DNA crystals compared to those of Au and Ni. For Ln3+-DNA crystals on an FET with either a Cr or Ni electrode at a fixed Vds, Ids decreased with increasing Vg ranging from −2 to 0 V and from 0 to +3 V in the positive and negative regions, respectively. By contrast, Ids for Ln3+-DNA crystals on an FET with Au decreased with increasing Vg in only the positive region due to the greater electronegativity of Au. Furthermore, Ln3+-DNA crystals on an FET exhibited behaviour sensitive to Vg due to the appreciable charge carriers generated from Ln3+. Finally, we address the resistivity and the mobility of Ln3+-DNA crystals on an FET with different metal electrodes obtained from Ids–Vds and Ids–Vg curves. The resistivities of Ln3+-DNA crystals on FETs with Cr and Au electrodes were smaller than those of pristine DNA crystals on an FET, and the mobility of Ln3+-DNA crystals on an FET with Cr was relatively higher than that associated with other electrodes.

Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET

In this paper, the performance of asymmetric underlapped FinFETs (U-FinFETs) is analyzed for linearity and harmonic distortion at high temperatures. The harmonic distortion that arises as a result of non-linear device characteristics requires a detailed analysis for better RF reliability performance. The variations in linearity and distortion characteristics with temperature are analyzed with regards to the primary components of harmonic distortion, second order distortion (HD2), third order distortion (HD3), and the total harmonic distortion (THD). For detailed understanding of the distortion characteristics of U-FinFETs, different device parameters such as the drain current (Ids) and transconductance (gm) are also analyzed. The results of the analysis suggest that the U-FinFETs present a significant reduction in harmonic distortion at elevated temperatures under subthreshold regime and restrict the degradation in harmonic distortion in the superthreshold regime resulting in better reliability for RF applications.

A top-gate GaN nanowire metal–semiconductor field effect transistor with improved channel electrostatic control

A uniformly n-type doped GaN:Si nanowire (NW), with a diameter of d = 90 nm and a length of 1.2 μm, is processed into a metal-semiconductor field effect transistor (MESFET) with a semi-cylindrical top Ti/Au Schottky gate. The FET is in a normally-ON mode, with the threshold at −0.7 V and transconductance of gm ∼ 2 μS (the transconductance normalized with NW diameter gm/d > 22 mS/mm). It enters the saturation mode at VDS ∼ 4.5 V, with the maximum measured drain current IDS = 5.0 μA and the current density exceeding JDS > 78 kA/cm2.

Degradation of pMOSFETs due to hot electron induced punchthrough

This paper proposes a method which can separate the parasitic effect from the drain current Id vs. gate voltage Vg curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An Id vs. Vg curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of Id vs. channel width W at each Vg to W=0μm. The Id vs. Vg curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage Vth of the parasitic MOSFET but increased Vth of the main MOSFET. These two opposite behaviors of Vth resulted in little HEIP-induced shift of Vth at W=2.5μm. |Vd| to secure ten-year HEIP lifetime of 10% shift of Vth was ≤2.2V at W=0.3μm, ≤3.5V at W=1.0μm, and ≤3.6V at W=10μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.

Quasi-free-standing bilayer epitaxial graphene field-effect transistors on 4H-SiC (0001) substrates

Quasi-free-standing epitaxial graphene grown on wide band gap semiconductor SiC demonstrates high carrier mobility and good material uniformity, which make it promising for graphene-based electronic devices. In this work, quasi-free-standing bilayer epitaxial graphene is prepared and its transistors with gate lengths of 100 nm and 200 nm are fabricated and characterized. The 100 nm gate length graphene transistor shows improved DC and RF performances including a maximum current density Ids of 4.2 A/mm, and a peak transconductance gm of 2880 mS/mm. Intrinsic current-gain cutoff frequency fT of 407 GHz is obtained. The exciting DC and RF performances obtained in the quasi-free-standing bilayer epitaxial graphene transistor show the great application potential of this material system.

Temperature Dependent Characteristics of InAlN/GaN HEMTs for mm-Wave Applications

This work presents a 100 nm-gate InAlN/GaN HEMT with current-gain cutoff frequency (fT) up to 120 GHz at room temperature (25°C). Temperature dependent DC and RF characteristics are measured from 25°C to 200°C. The maximum drain current (Id−max) decreases from 1247 mA/mm to 927 mA/mm as the temperature increases from 25°C to 200°C. For maximum fT, it drops to 87 GHz and 64 GHz at 100°C and 200°C respectively. These results show that although both DC and RF performances decrease with the increase in temperature, the device still exhibits high mm-wave performance at high temperatures. Thus, InAlN/GaN based HEMTs are very promising for high temperature mm-wave applications.

Influence of Electrical Modes on Sensitivity of MISFET Ionizing Radiation Dose Sensors

The influence of electrical modes on the radiation sensitivity of the sensors based on the metal-silicon dioxide-semiconductor field-effect transistor (RadFET) was experimentally investigated. The RadFETs were fabricated by means of conventional MOS-technology. There were measured the RadFET-based microdosimeter output voltages Vout as function of the X-rays radiation doses D for different drain currents ID and source-drain voltages VD. It was shown how the conversion function Vout(D) and the radiation sensitivity SD are depending on electrical modes. To interpret experimental data there were presented the models based on calculations the dependences of threshold voltage VT and specific slope (transconductance) b vs. D. These dependences were calculated from the experimental ID–VG characteristics measured before, during and after irradiations (value VG is the gate voltage).

Effect of Pressure and Hot Filament Cathode on Some Plasma Parameters of Hollow Anode Argon Glow Discharge Plasma

The present study represents a review article and a complementary study to a published paper of direct current hot cathode and hollow anode argon glow discharge plasma at different pressures in the range 0.05 - 0.8 mbar. The glow discharge usually obtained by applying a high voltage between the electrodes sufficient to occurring breakdown of argon gas and sustaining the discharge. Additional estimation of some plasma parameters, ion temperature, degree of ionization and electron energy distribution function as well as some characteristics of glow discharge under the influence of pressure and filament current has been done. Plasma parameters have been calculated using single probe method at fixed discharge current Id=1.88mA and diameter of hollow anode. Furthermore a computer MATLAB program is applied for this purpose. Results show that the average discharge voltage increases while its average discharge current decreases according to the increasing of the filament current. On the Contrary the average discharge voltage decrease nearly exponentially whiles its average discharge current increases according to increasing of the gas pressure. Degree of ionization starts to increase from low pressure to medium and then tends to decrease toward high pressure investigated. However it starts to increase to maximum value at filament current 0.9A then tends to decrease at higher current and low pressure. While for high pressures there is no significance change. Ion temperature increases slowly with filament current up to 0.9A and then sharply increases to maximum value at 1.5A. But it decreases for pressures in the range 0.05 - 0.09 mbar and then increases with gas pressure. Electron energy distribution function (EEDFs) decrease according to increases filament current, however, it starts to increase from low pressure to maximum value at medium pressure then tends to increase according to further increases of pressure.

Impact of AlN Spacer on Analog Performance of Lattice-Matched AlInN/AlN/GaN MOSHEMT

In this work, a detailed investigation of the impact of spacer layer thickness on analog performance of an AlInN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT) is carried out. A thorough analysis of the key figure-of-merits such as threshold voltage (Vth), two-dimensional electron gas sheet charge density (ns), drain current (Id), transconductance (gm), and gate leakage current are performed for various spacer thicknesses ranging from 0.5 nm to 1.8 nm. From the two-dimensional ATLAS device simulation results, it is observed that the performance of AlInN/AlN/GaN MOSHEMT is affected by the variation of spacer thickness. Also, we have developed mathematical expressions for the evaluation of Vth, ns, Id, gm and gate leakage current for the proposed device. The model results and technology computer-aided design simulation results are verified and also found to be satisfactory. Improved sheet charge density and superior analog performance is observed due to the insertion of the AlN spacer. Suppression in the forward gate current is observed due to the insertion of the AlN spacer which made it possible to apply a high gate voltage in the transistor operation. From the fabrication point of view, it is also feasible to utilize the existing complementary metal–oxide–semiconductor process flows to fabricate the proposed device.

Impact of gate dielectric constant variation on tunnel field-effect transistors (TFETs)

The influence of gate dielectric constant variation on tunnel field-effect transistors (TFETs) has been investigated. High-κ materials in polycrystalline nature induce localized gate dielectric constant variation. According to the simulation results, TFETs show larger standard deviation of threshold voltage (Vth), subthreshold swing (SS) and saturation current (Id,sat) than metal–oxide–semiconductor FETs (MOSFETs). It has been revealed that local gate dielectric constant variation should be considered to evaluate the total variation of TFETs. This is because the gate insulator near the source region dominates TFET performance. Also, the ideas have been proposed in order to reduce the gate dielectric constant variation.

The ultraviolet responses of ZnO-based thin-film transistor prepared by sol–gel method

Bottom-gate and top-contact thin-film transistors with ZnO film as a channel layer were fabricated by sol–gel method. The structural and optical properties of the deposited ZnO films were investigated through X-ray diffractometer, scanning electron microscopy and UV–Vis spectrophotometer. ZnO film has a high absorption in the ultraviolet region and c-axis orientation normal to the substrate. The on/off current ratio, channel mobility and threshold voltage of ZnO-based thin-film transistors in dark are 105, 0·02 cm2 V−1 s−1 and 8·3 V, respectively. Under UV light illumination (λ = 365 nm) with an intensity of 2·4 μW/cm2, the drain–source current IDS of thin-film transistor dramatically increases and the photo-to-dark current ratio is greater than 104. The transient response of the device to ultraviolet illumination is also discussed. The results may open the possibility of employing ZnO-thin-film transistors as UV photodetector.

Spin-dependent transport properties of a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor structure

We fabricate a vertical spin metal-oxide-semiconductor field-effect transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current IDS by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate IDS by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale.

Label-free electronic detection of interleukin-6 using horizontally aligned carbon nanotubes

A facile, sensitive, and label-free assay for detection of interleukin-6 (IL-6) using liquid-gated field-effect transistor (FET) sensors based on horizontally aligned single-walled carbon nanotubes (SWCNT) is proposed. This approach relies on the drain current (Id) responses of the transistor upon interactions of IL-6 with its corresponding antibody (IL-6R) immobilized on SWCNT. The proposed immunosensor exhibits superior sensitivity (limit-of-detection=1.37pg/mL) in virtue of the reduced tube-to-tube contact resistance, good selectivity (no responses to bovine serum albumin and cysteine were observed and detection of target molecules in serum was achieved) as a result of the highly specific interaction between IL-6 and IL-6R, and excellent stability (no significant degradation in the electronic performance after storage under ambient conditions for up to 3months) in virtue of the strong adhesion of CNT to the quartz substrate and good horizontal alignment of these tubes. Therefore, the proposed immunosensor is a promising platform for early diagnosis of various diseases (including some cancers) that can be indicated by the circulating level of IL-6.

Dual Gate Tunable and High Responsivity Graphene‐Based Field Effect Transistors

SummaryThe output characteristics of a dual gated depletion mode, n‐channel graphene field effect transistor (n‐Gr‐FET) are simulated to understand the unipolar Ids–Vds behavior for different values of gate voltages, (Vback and Vtop). In our results, the saturated drain‐source current (Ids) varies from 0.001 to 100 µA/µm, 9 to 125 µA/µm and 16 to 135 µA/µm as Vback is varied from 5 to 40 V with correspondingly Vtop of 0, 2 and 10 volts. Consequently, there is four to eight times enhancement in estimated mobility for varying Vback from 5 to 40V. The unipolar saturation in Ids at higher values of Vds can be understood from the compensation of parallel Vds and transverse (Vback−Vtop) electric fields. Furthermore, the channel length modulation (increase in Ids for Vtop > 0) supported by the increase in mobility, is observed because of reverse junction formation at the vicinity of the drain and gate terminal. The results signify that the dual gated n‐Gr‐FET, at optimum Vback, modulates the unipolar characteristics in channel region. Thus, making n‐Gr‐FET a potential candidate to stipulate the demand of low power, high performance functionalities in nano‐electronic applications.

Analog/RF performance of AlInN/GaN underlap DG MOS-HEMT

This work uncovers the potential benefit of AlInN/GaN underlap double-gate MOS-HEMT for RF and analog applications. The device channel consists of a lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-K Al2O3 as the gate dielectric. The 2D Sentaurus TCAD simulation is done using the hydrodynamic model and interface traps are considered. The simulation model was calibrated with the previously reported experimental result. A comprehensive, quantitative investigation of key analog and RF figures-of-merits (FOMs) is done for a wide range of gate length (Lg), underlap length (Lun) and barrier thickness (TB). Scaling of Lg and Lun leads to increase in the drain current (Id), transconductance (gm), cutoff frequency (fT) and max frequency (fmax) but, at the expense of the reduced transconductance generation factor (gm/Id), gain and output resistance (Ro). Large improvement in almost all analog and RF FOMs was observed for scaled Lg and Lun. Devices with thinner barrier thickness exhibited improved gm, TGF, Ro, fT and fmax. Simulations have revealed a very high drain current of 5.26 mA/μm, peak gm of 5.34 mS/μm, and a maximum gain of 47 dB. The peak values of fT and fmax, extracted from two port Y-parameters, were found to be 786 GHz and 832 GHz, respectively for highly scaled device. These results demonstrate the potential of AlInN/GaN underlap MOS-HEMT for high power and high-frequency applications.

Modernization of cathode assemblies of electron sources based on low pressure arc discharge

The paper presents modified cathode assemblies, including their main characteristics, for plasma electron sources based on a constricted low-pressure arc initiated by a discharge in crossed electric and magnetic fields. One of the modified cathode assemblies allows the electrode system of the auxiliary discharge to operate at a pressure of ≈ 0.3 Pa, as against ≈ 10 Pa before the modification, provides a larger diameter constriction of the pulsed (up to τ = 250 μs) arc, and thus extends the range of operating currents for the plasma-cathode discharge system up to Id = 300 A. The other modified assembly operates at widely varying discharge currents Id = 5-100 A, provides lesser amounts of cathode microdroplets at the discharge electrodes, and allows the arc to operate at comparatively low voltages. The use of cathode assemblies adapted for specific discharge systems extends the capabilities of plasma- emitter electron sources as well as the range of their applications in scientific and technological fields.

High switching speed copper phthalocyanine thin film transistors with cut-off frequency up to 25 kHz

The characteristics of high frequency and high speed are demonstrated in vertical structure organic thin film transistors (VOTFTs) fabricated by DC magnetron sputtering and vacuum evaporation. The saturated current–voltage characteristics can be determined by drain-source negative bias voltage. Responsive frequency of the device is as high as 20 kHz when rectangular wave dynamic signal is applied to the gate-source electrode, and switch characteristic time reaches the microsecond. The unsaturated current–voltage characteristics are observed when the drain-source bias voltage is positive. In the condition of VDS = 3 V and VGS = 0 V, the drain-source current IDS is 2.986 × 10−5 A, and the current density is 1.194 mA/cm2. Cut-off frequency fc is 25 kHz when a small sine wave dynamic signal is applied to the gate-source electrode. The volt-ampere characteristic of VOTFTs transfers from linear to nonlinear with increasing of drain-source bias voltage.