Current-controlled Oscillator Research Articles

Readout Circuit Design for RRAM Array-Based Computing in Memory Architecture

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages.

A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC

This paper presents a novel subranging Sigma-Delta ADC using a relaxation Current-Controlled Oscillator (ICO). The instantaneous frequency of the ICO at the sampling instant determines its time resolution and hence its quantization error, while its average frequency determines its power dissipation. Therefore, running the ICO at nominally lower frequency for most of the sampling period while increasing its frequency close to the sampling instant achieves high resolution and low power consumption. This idea is similar to the strategy employed by athletes in a race where they speed-up close to the finish line to gain a clear lead from others. A prototype ADC is designed and fabricated in TSMC 180nm CMOS technology. It achieves an ENOB of 11.9 bits consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10~\mu \text{W}$ </tex-math></inline-formula> of power from a 1.8V supply and occupies an active area of 0.06 mm 2, which corresponds to a Schreier FoM of 156.8 dB and a Walden FoM of 625 fJ/conversion cycle.

Research on the Commissioning Method of a Current-controlled Oscillator

In this paper, the commissioning method of the current-controlled oscillator (ICO) is researched, making the ICO work under the required amplitude and frequency and exploring the best phase noise performance of ICO under the constraints of power dissipation and area. Through the theoretical analysis and simulation experiments, the commissioning process of ICO is clarified, which can meet the basic indexes of ICO, especially the amplitude and frequency, and optimize the phase noise performance of ICO.

A 0.8–3.2 GHz PLL with wide frequency division ratio range

An improved phase-locked loop (PLL) with a wide frequency division ratio range is presented. A digital to analog converter (DAC) is used to separate the proportional path and integral path, thus the dynamic performance of PLL can be flexibly adjusted by DAC and the current-controlled oscillator (CCO). As the resistor in the second-order PLL is replaced by an equivalent circuit, the implemented PLL is insensitive to the process, voltage, and temperature (PVT) variation. Decoupling the relationship between loop bandwidth ωb and division ratio N improves the overall performance over a wide dynamic output frequency range. The PLL was implemented in TSMC 22 nm CMOS process and the chip occupies an area of 0.04 mm2. The measured output frequency is ranged from 0.8 GHz to 3.6 GHz. The phase noise is −107.3dBc@1 MHz and the integrated RMS jitters at 1.92 GHz is 3.36ps. The total power consumption at 1.92 GHz is 4.2 mW.

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

We present a 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> pitch and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization technique for CCO is introduced, which increases the maximum CCO frequency beyond 3 GHz, while ensuring accurate on-chip matrix–vector multiplications (MVMs). Moreover, the design and functionality of the digital ADC calibration procedure is described in detail and the MVM accuracy is quantified. Finally, the measured classification accuracies of deep learning (DL) inference applications on the MNIST and CIFAR-10 datasets, when two IMC cores are employed, are presented. For a performance density of 1.59 TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a measured energy efficiency of 10.5 TOPS/W, at a main clock frequency of 1 GHz, is achieved.

A 700-μm², Ring-Oscillator-Based Thermal Sensor in 16-nm FinFET

Temperature monitoring and regulation is a critical power/performance feature in microprocessors. Due to the multiplicity of hotspots, a large number of on-die sensors are utilized. This requires them to be highly compact, low energy and fast. A miniaturized current controlled oscillator (CCO) sensor is described for this application. It has an area of only 700 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}^{2}$ </tex-math></inline-formula> in the 16-nm FinFET process, with an energy consumption of 0.25 nJ in a 6.9- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> conversion. The inaccuracy is within ±1.5 °C peak-to-peak (p-p) over a 130 °C range, at a resolution of 0.32 °C. These characteristics make the circuit attractive for high-density thermal sensing.

Sub-Milliwatt Transceiver IC for Transcutaneous Communication of an Intracortical Visual Prosthesis

An intracortical visual prosthesis plays a vital role in partially restoring the faculty of sight in visually impaired people. Reliable high date rate wireless links are needed for transcutaneous communication. Such wireless communication should receive stimulation data (downlink) and send out neural recorded data (uplink). Hence, there is a need for an implanted transceiver that is low-power and delivers sufficient data rate for both uplink and downlink. In this paper, we propose an integrated circuit (IC) solution based on impulse radio ultrawideband using on-off keying modulation (OOK IR-UWB) for the uplink transmitter, and binary phase-shift keying (BPSK) with sampling and digital detection for the downlink receiver. To make the solution low-power, predominantly digital components are used in the presented transceiver test-chip. Current-controlled oscillators and an impulse generator provide tunability and complete the on-chip integration. The transceiver test-IC is fabricated in 180 nm CMOS technology and occupies only 0.0272 mm2. At 1.3 V power supply, only 0.2 mW is consumed for the BPSK receiver and 0.3 mW for the IR-UWB transmitter in the transceiver IC, while delivering 1 Mbps and 50 Mbps, respectively. Our link budget analysis shows that this test chip is suitable for intracortical integration considering the future off-chip antennas/coils transcutaneous 3–7 mm communication with the outer side. Hence, our work will enable realistic wireless links for the intracortical visual prosthesis.

Ring-Oscillator with Multiple Transconductors for Linear Analog-to-Digital Conversion

This paper proposes a new circuit-based approach to mitigate nonlinearity in open-loop ring-oscillator-based analog-to-digital converters (ADCs). The approach consists of driving a current-controlled oscillator (CCO) with several transconductors connected in parallel with different bias conditions. The current injected into the oscillator can then be properly sized to linearize the oscillator, performing the inverse current-to-frequency function. To evaluate the approach, a circuit example has been designed in a 65-nm CMOS process, leading to a more than 3-ENOB enhancement in simulation for a high-swing differential input voltage signal of 800-mVpp, with considerable less complex design and lower power and expected area in comparison to state-of-the-art circuit based solutions. The architecture has also been checked against PVT and mismatch variations, proving to be highly robust, requiring only very simple calibration techniques. The solution is especially suitable for high-bandwidth (tens of MHz) medium-resolution applications (10–12 ENOBs), such as 5G or Internet-of-Things (IoT) devices.

A 8800 μm² CCO-Based Voltage-Droop and Temperature Detector in 65 nm

The Vcc level and temperature of IC’s are important parameters which determine the power/performance. Resonances in the package and platform can cause significant AC voltage droops which can degrade functionality, requiring additional guard-band. Prior-art droop detectors utilize digital delay circuits, such as tunable replica circuits to measure these droops. However, the delay is a strong function of temperature as well as the DC Vcc level, making it difficult to differentiate the AC droop across different voltage and temperature levels. It is proposed to utilize a current controlled oscillator (CCO) with an analog bias to mitigate the voltage and temperature dependencies, such that only the AC droop is measured. The CCO frequency is independent of the DC Vcc level, while the temperature is also characterized along with the AC droop, such that both temperature and droop levels can be extracted. The sensor can measure droops and temperature to an accuracy of 10mV and ± 3 °C respectively. The circuit occupies $8800~\mu \text{m}^{2}$ in 65nm with a power consumption of $297~\mu \text{W}$ . This circuit is very useful to characterize the power grid in design for test (DFT) applications as well as on-the-fly real time chip operation.

A 0.11–0.38 pJ/cycle Differential Ring Oscillator in 65 nm CMOS for Robust Neurocomputing

This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about 11% compared with the conventional one without degrading the phase noise. Alternatively, the power consumption can be reduced 15% at the same frequency. The prototype structures are fabricated in a standard 65 nm CMOS technology and measurements demonstrate that the proposed CCO operates from 0.7 - 1.2 V supply with maximum frequencies of 80 MHz and energy/cycle ranging from 0.11 - 0.38 pJ over the tuning range. Further, system level simulations show that the nonlinearity in current-frequency conversion by the CCO does not affect its use as a neuron in a Deep Neural Network if accounted for during training.

Efficient detection of transistor stuck-on faults in CMOS circuits using low-overhead single-ended ring oscillators

Very large-scale integration technology is accelerating the growth and prevalence of nanoscale devices worldwide, but at the same time facing technical challenges in terms of fault detection due to the compact size of chips. Thus, the detection of faults in chips caused by limitations of the manufacturing process or operational aspects of the architecture is obligatory to assess the effective performance of devices. In this paper, two single-ended ring oscillator (SERO)-based transistor stuck-on (TSON) fault detection methods are proposed for complementary metal–oxide–semiconductor (CMOS) circuits. The SERO is used as a current-controlled and voltage-controlled oscillator in method 1 and 2, respectively, reducing the circuit overhead of the detection block. Simulations are carried out using Cadence Virtuoso in 90-nm technology. The results show that both methods can successfully detect TSON faults in CMOS circuits based on the oscillatory behavior of the SERO. Moreover, these methods avoid the need to sense the output voltage level or quiescent current, which increases the possibility of successful fault detection, especially for submicron-level structures by avoiding improper logic and unreliable current values. Test vectors and fault locations can also be easily identified using the proposed methods, reducing the implementation complexity of CMOS fault detection techniques.

A Sleep Apnea Monitoring IC for Respiration, Heart-Rate, SpO2 and Pulse-Transit Time Measurement Using Thermistor, PPG and Body-Channel Communication

This paper presents a low power bio-signal acquisition system for sleep apnea, which can measure respiration, heart rate, SpO2, and pulse transit time (PTT). For respiration, a nasal airflow sensor with a thermistor is used. For PTT that can serve as a surrogate for blood pressure during sleep, two photoplethysmogram (PPG) sensors are employed at the upper arm and the finger. For improved comfort during sleep, body channel communication (BCC) is used to remove long wires. To reduce power consumption and circuit complexity, sensor’s analog front-end is implemented by using a current-controlled oscillator which is also shared by BCC transmitter that employs analog frequency modulation. Implemented in $0.18~\mu \text{m}$ CMOS, the proposed IC consumes less than 3.6 mW from a 1.8 V supply, while occupying 0.145 mm2 of active area.

A Novel Current-Controlled Oscillator-Based Low-Supply-Voltage Microbolometer Readout Architecture

In this paper, we present a novel, almost-digital approach for bolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in the classical readout circuits. This approach, which has not been reported before, both produces the required gain in the bolometer input circuit and directly digitizes the bolometer signal. With the proposed architecture, the need for large capacitances (of the order of 10–15[Formula: see text]pF for each column) at which the current is accumulated in the bolometer circuits and the voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design readout circuits with reduced pixel pitch and lower power supply, both of which in turn lead to higher-resolution Focal Plane Arrays (FPAs) with lower power dissipation. The new architecture is modeled and simulated using a 180-nm CMOS process for sensitivity, noise performance, and power dissipation. Unlike the 3.3-V power supply usage of classical readout circuits, the proposed design utilizes 1.2-V analog and 0.9-V digital supply voltages with a power dissipation of almost half of the classical approach.

A Compact Temperature Sensor with a Resolution FoM of 1.82 pJ·K2

In this article, a compact ultralow-power smart temperature sensor realized in 130-nm standard CMOS technology, provided by STMicroelectronics, is presented. The sensor is designed with the aim of measuring local temperature variations in the range of −20 °C–85 °C in temperature drift compensation applications. It relies on a simple circuit topology that employs two current-controlled oscillators—a divider and a 15-bit counter—which allows temperature-to-digital conversion. Experimental results show an inaccuracy of ±0.6 °C ( $3\sigma$ ) and a resolution of 0.012 °C with power consumption as low as $6~\mu \text{W}$ at 1.3-V power supply with a total die area of only 0.00916 mm2.

60 pW 20 μm size CMOS implementation of an actual soma membrane

The article presents a 65 nm technology implementation of a low-power artificial spiking neuron intellectual property (IP) core. The concept of the circuit is based on modeling the mechanism of a perikaryon membrane and the propagation of the action potential in an axon. Nerve impulses are generated using a current-controlled oscillator. Thanks to this oscillator, the circuit is implemented exclusively using metal-oxide semiconductor transistors, with the omission of capacitors. The main advantage of the presented implementation is the possibility of implementing the IP-core using nanometer digital complementary metal-oxide semiconductor technologies with the possibility of placing it within a common substrate with a digital processor. The circuit operates in weak-inversion mode with a 0.3 V power supply and does not require additional polarization voltages. The maximum frequency of impulse generation equals 2.5 kHz. The paper describes two operating modes of the circuit: a cortical mode with power consumption of 60 pW and a processing mode with power consumption of 52.2 pW. The power reduction was obtained using a circuit structure in which the power supply current consumption is reduced with the moment the circuit starts processing. The article also contains results of a process–voltage–temperature analysis.

A Single-Event Transient-Tolerant High-Frequency CMOS Quadrature Phase Oscillator

High-frequency oscillators developed in CMOS technologies for space applications are vulnerable to single-event transient (SET) effects caused by ionizing radiation strikes. We have designed a phase-locked loop (PLL) with a quadrature phase current-controlled oscillator (QCCO) to overcome this limitation. The feedback mechanism in the QCCO helps in improving the SET tolerance, while parallel coupling achieves wide tuning range. The oscillator is irradiated with laser pulses at a certain pulse repetition frequency, which results in spurious tones in the oscillator output spectrum. The strengths of these spurs are used for evaluating the SET tolerance of the oscillator. Under identical conditions, experiments show that the QCCO has an average of 15-dB lower spur level compared to a conventional single-phase $LC$ voltage-controlled oscillator (SVCO) and an SVCO-based PLL loses lock at a certain laser pulse energy, while the QCCO-based PLL remains in the locked state. These results confirm that the QCCO significantly improves the reliability of high-frequency PLLs in radiation environments.

Toward High Throughput Core-CBCM CMOS Capacitive Sensors for Life Science Applications: A Novel Current-Mode for High Dynamic Range Circuitry.

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.

Crystal‐less oscillator calibration using serial data as frequency reference

A frequency calibration method for a crystal-less current-controlled ring oscillator is presented. It uses a serial data signal from another chip as the frequency reference. The proposed calibration circuit is composed of the coarse calibration and the fine calibration circuit. The coarse calibration circuit controls a binary weighted biasing current source array, while the fine calibration circuit generates a pulse-width-modulation (PWM) signal to control a switched biasing current source. The duty cycle ratio of the PWM signal is obtained by measuring the frequency ratio error between the oscillator output and the reference signal. An auto-correlation-based method is proposed to calculate the frequency ratio error. The 8 MHz ring oscillator in together with the calibration circuit has been fabricated in a 0.13 μm CMOS process. Measured results on 24 chips show that the relative frequency error is reduced to 0.0239% (mean offset + 3σ) after calibration. The reported oscillator shows advantages in accuracy, power consumption and chip area.

A Highly Digital Second-Order Oversampling TDC

A second-order, single loop ΔΣ time-to-digital converter (TDC) is presented in this letter. The proposed TDC uses two differential current-controlled oscillators as phase domain integrators. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Digital differentiation using XOR implements an intrinsic first-order high-pass shaping of static element mismatch in the current steering digital-to-analog converter. A prototype TDC in 65-nm CMOS process has linearity of 8.1 bits, integrated noise of 3.8 ps and energy efficiency of 0.45 pJ/code over a bandwidth of 2.5 MHz.

Design of active inductor-based current-controlled oscillators using gm/Id methodology

This paper presents a novel design procedure based on gm/Id methodology to achieve a trade-off between tuning range, phase noise and output swing of active-inductor-based current-controlled oscillators (CCOs). It is shown that equations for the phase noise and corner frequency of the selected CCO configuration are related to the gm/Id parameters. In accordance with the above relations, the designed CCO is simulated using 0.18 µm TSMC CMOS technology parameters. The simulation exhibits a tuning range of 432 MHz to 3.54 GHz, a phase noise in the range of −84 dBc/Hz to −104.6 dBc/Hz at 1 MHz offset from carrier and a figure of merit of 178.4 dB in 1.453 GHz.