Current Conduction Path Research Articles

A Three-Phase Single-Sensor-Based Cuk-Derived PFC Converter With Reduced Number of Components for More Electric Aircraft

A new three-phase Cuk-derived power factor corrected (PFC) converter with only three switches for more electric aircraft is presented. The proposed converter benefits limited components for its operation, and only one semiconductor from each phase is in the current conduction path throughout the converter operation that substantially reduces the conduction losses leading to high efficiency and low converter thermal management. Further, the control effort required for converter operation is very less as all the three switches are driven by one gate signal. The converter output inductors are designed for discontinuous current operation for the entire converter power range to realize natural PFC at ac power source. The converter control is very simple, economical, and reliable since only one sensor is required for implementation. A detailed discussion on the converter steady-state operation for one switching cycle is presented. The converter small-signal model and the design expressions are derived to ease the converter control and the design. Further, the feasibility of the proposed scheme and the design are validated with the experimental results from a 2-kW laboratory prototype.

Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance

In this paper, a novel bulk silicon lateral superjunction double diffused MOSFET (SJ-LDMOS) with dual gate (DG) is proposed and its mechanism is investigated by numerical TCAD simulations. The proposed structure features the combination of a trench gate and a planar gate, forming two current conduction paths. One current conduction takes place along the highly doped N-pillar. The other is through the N-buffer layer ensuring uniform current distributions, which solves the problem of low conduction in the N-buffer layer of the SJ-LDMOS structures. The dual conduction paths improve the current uniformity through the entire SJ layer and the N-buffer layer, which effectively reduces the resistance of the device. Simulation results indicate that the proposed device is predicted to achieve a high breakdown voltage (BV) of 643 V and an extremely low specific ON-resistance (R ON,sp ) of 28.53 mΩ·cm 2 , which is by 46.7 % lower than that of the previously N-buffer SJ-LDMOS structures with the same drift length. Besides, the transconductance of DG SJ-LDMOS is increased by 54.5 % and the figure of merit (FOM) on BV 2 /R ON,sp of DG SJ-LDMOS is increased by 85.5 %.

Diagnosis method of open-circuit fault for T-type three-level inverter based on residual voltage

Multilevel inverter topologies have been widely used in applications of wide-power range and fault diagnosis of such circuits is becoming more and more important. T-type three-level inverters have advantages in efficiency compared to common neutral-point-clamped inverters. This paper proposes a new diagnosis method of an open-circuit (OC) fault for a T-type three-level inverter. The method is implemented by measuring the phase voltage of the circuit and comparing it with the reference voltage of the circuit to obtain a residual voltage. Firstly, according to the analysis of different current conduction paths of the circuit, the voltage level changes of the circuit bridge voltage and phase voltage in different device open modes are studied. Then, based on the above analysis, a device open-circuit fault diagnosis scheme is proposed based on the residual voltage. Finally, simulation and experimental results show that the proposed method can identify the faulty switch exactly and quickly.

A Nine-Level Inverter for Low-Voltage Applications

A novel nine-level inverter topology for low-voltage applications is proposed in this paper. Each phase of the inverter is composed of a T-type three‐level cell and an active neutral point clamp three‐level cell. The operation principles and current conduction paths are analyzed in detail and phase-disposition sinusoidal pulsewidth modulation is used to balance voltages of flying capacitors and neutral point. The mathematical relationship between the capacitance and the desired ripple in the inverter output is established to select the intermediate capacitance value. Compared with other nine-level inverters suitable for low-voltage applications, the proposed inverter has advantages in a number of gate drivers, a number of dc sources, and efficiency. Simulation and experimental results under different settings of modulation index, power factor, output frequency, and load are presented to verify the effectiveness and performances of the proposed inverter.

Radiation-Tolerant p-Type SnO Thin-Film Transistors

This present work investigated the effects of proton-beam irradiation on SnO-based p-type oxide thin-film transistors (TFTs) for the first time. The experiments were performed using a 5-MeV proton beam with doses ranging from $10^{12}$ to $10^{14}\,\,\textsf {p}\cdot \textsf {cm}^{-2}$ . The experimental results showed that the transfer curves of the p-type SnO TFT rarely changed following the proton irradiation at every irradiation condition, indicating that the p-type SnO TFT could be potentially useful in implementing complementary-logic-based oxide TFT circuits operating in harsh environments. The insensitivity of current conduction paths to SnO lattice disorder was considered as a possible mechanism for the observed radiation tolerance of the p-type SnO TFTs.

Effects of Fluorine Plasma Treatment on Au-Free Ohmic Contacts to Ultrathin-Barrier AlGaN/GaN Heterostructure

Effects of fluorine plasma etching on Au-free ohmic contacts to SiNx-passivated ultrathin-barrier AlGaN/GaN heterostructure were investigated. It is found that overetching of SiNx passivation layer, which was grown by low-pressure chemical vapor deposition (LPCVD), resulted in strong accumulation of fluorine at the junction between ohmic metal, SiNx passivation, and the (Al)GaN barrier layer. The possible depletion effect of fluorine will cutoff the current conduction path between the ohmic metal and the 2-D electron gas (2DEG) in the access region, leading to degraded contact resistance and 2DEG sheet resistance. The Au-free ohmic contact mechanism can be well fitted by thermionic field emission model, and the extracted Schottky barrier height is increased by ~0.038 eV with F overetching.

High performance enhancement-mode HEMT with 3DEG to conduct current and 3DHG as back barrier

Abstract A novel enhancement-mode (E-mode) high electron mobility transistor (HEMT) with three-dimensional electron gas (3DEG) and three-dimensional hole gas (3DHG) is presented. It features a GaN-top layer, a positive graded AlGaN barrier layer (GAL), and a negative graded AlGaN back barrier layer (GABL) (wherein the positive/negative doping gradient is defined with respect to the growth direction), with a vertical conduction channel aside a MIS trench gate. The 2DHG is formed at the interface between the GaN-top layer and GAL. The 3DEG and 3DHG are formed due to the polarization induced by linearly grading Aluminum (Al) composition from 0 to xAl in GAL and 0.4 to 0 in GABL, respectively. The source and drain locate at the same side of the MIS trench gate, and the source contacts with the gate. Firstly, 2DHG blocks the electron current conduction path between the source and 3DEG so as to achieve E-mode. Secondly, the high-sheet density 3DEG in GAL greatly increases the on-state current. Thirdly, the leakage current effectively is reduced by the 3DHG in GABL, improving the breakdown voltage. Fourthly, a high breakdown voltage (BV) is obtained because the polarization junction formed by the polarization charges in GAL and GABL improves the electric field distribution in the drift region. The BV of the proposed HEMT increases to 1080 V from 47 V of the conventional MIS HEMT at the same length of the drift region, and specific on-resistance (Ron,sp) decreases to 0.29 mΩ cm2 from 0.64 mΩ cm2 in simulation.

A Current Reconstruction at Parallel Three Phase Inverters Using Two Current Sensors

In this paper, a current restoration method which can be applied to three phase parallel interleaved inverters (TPPII) using two current sensors has been proposed. In the proposed current reconstruction method, the branch current and the phase current of the two phases of the TPPII are sampled concurrently at the peak and valley of the pulse width modulation (PWM) carrier using two hall-effect sensors. Then, the phase current of each inverter is reconstructed by analyzing the sensed current with the current conduction path information according to the switch state in the peak and valley of the PWM carrier. This paper additionally analyzes the characteristics of the offset occurring in the detection process of two current sensors and it proposes a compensation method to reduce the offset on-line. In order to at once reduce the offset of the three-phase recovery current caused by the DC offset of the sensor, a coordinate conversion method and a low pass are used. To verify the performance of the proposed current recovery method and real-time offset compensation method, a simulation using PSIM software was performed, and experiments were conducted using a three phase parallel inverter composed of insulated gate bipolar transistor (IGBT) modules. In particular, the AC offset that occurred in the sampling process during the experiment was analyzed and modeled, and it was reduced by simple calculation.

High Step-Up Y-Source Coupled-Inductor Impedance Network Boost DC–DC Converters With Common Ground and Continuous Input Current

High step-up Y-source coupled-inductor impedance network boost dc–dc converter with common ground and continuous input current is presented in this paper. The proposed converter has added auxiliary diodes and capacitors to three-winding Y-shaped coupled-inductor cells to constitute the current conduction path and realize the voltage-double function. Compared to other magnetically coupled boost converters, the proposed converter can produce the higher voltage gain with more degrees of freedom in winding match. The same output gain can be obtained by using different winding turn ratios. Also, the proposed converter has a common ground and realizes the continuous input current. The corresponding topologies and steady operation principles are analyzed. The experimental results in a 300-W prototype have verified the validity of the theoretical analysis.

Evaluation Method of Flyback Converter Behaviors on Common-Mode Noise

Common-mode (CM) conduction electromagnetic interference (EMI) is a challenge for switched-mode power supply (SMPS) designers. A flyback converter is a traditional topology used in low-power isolated applications. The size and cost of EMI filters are important considerations for higher power density and lower cost of SMPS design. In most cases, the CM current is generated by voltage pulsation (dv/dt) assigned on the primary winding and the secondary winding. The CM current conduction paths can be mainly categorized into two categories. One is the interwinding parasitic capacitance of the transformer, and the other is the parasitic capacitance between the semiconductor switches and the protective ground. This paper proposed an evaluation method to measure the equivalent CM noise capacitance of the two main CM current conduction paths, respectively. Then, this paper proposed a CM noise cancellation scheme based on the transformer winding design combining the measurement technique and the FEM simulation tool. Planar transformers with PCB windings also have advantages in low profile, good heat dissipation, and good stray parameter consistency. Based on these considerations, an 18-W adapter is designed and tested to verify the effectiveness of the proposed evaluation method and the design scheme.

Bioelectrical Impedance and The Frequency Dependent Current Conduction Through Biological Tissues: A Short Review

Biological tissues are developed with biological cells which exhibit complex electrical impedance called electrical bioimpedance. Under an alternating electrical excitation the bioimpedance varies with the tissue anatomy, composition and the signal frequency. The current penetration and conduction paths vary with frequency of the applied signal. Bioimpedance spectroscopy is used to study the frequency response of the electrical impedance of biological materials noninvasively. In bioimpedance spectroscopy, a low amplitude electrical signal is injected to the tissue sample or body parts to characterization the sample in terms of its bioimpedance. The electrical current conduction phenomena, which is highly influenced by the tissue impedance and the signal frequency, is an important phenomena which should be studied to understand the bioimpedance techniques like bioelectrical impedance analysis (BIA), EIS, or else. In this paper the origin of bioelectrical impedance and current conduction phenomena has been reviewed to present a brief summary of bioelectrical impedance and the frequency dependent current conduction through biological tissues. Simulation studies are conducted with alternation current injection through a two dimensional model of biological tissues containing finite number of biological cells suspended in extracellular fluid. The paper demonstrates the simulation of alternating current conduction through biological tissues conducted by COMSOL Multiphysics. Simulation studies also show the frequency response of the tissue impedance for different tissue compositions.

Single-Phase DVR with Semi-Z-Source Inverter for Power Distribution Network

A novel topology of single-phase dynamic voltage restorer (DVR) is proposed to compensate the load voltage during voltage sag and voltage swell events. The semi-Z-source converter is utilised in its inverter operating mode for this proposed topology. The reduction in the number of active switches in the inverter and also in the current conduction path without compromising the output voltage range is the merit of the semi-Z-source inverter-based DVR against the commonly used full-bridge inverter-based DVR. The load voltage contains harmonics within the permissible limits when the compensation is performed by the semi-Z-source inverter-based DVR. The need for the filter circuit is eliminated; hence, the magnitude difference and the phase shift in the inverter output voltage due to the filter circuit are not present in the semi-Z-source inverter-based DVR. The proposed topology is cheap compared to the full-bridge inverter-based DVR topology. The simulations performed in MATLAB/Simulink environment are presented to validate the performance of the proposed topology. A comparison between the semi-Z-source inverter-based DVR and full-bridge inverter-based DVR is presented in this paper. The novel topology of DVR using semi-Z-source inverter is proved to be a better solution to the full-bridge inverter-based DVR.

Laboratory characterization and modeling of DC electrical resistivity of sandy soil with variable water resistivity and content

Soil resistivity is an important parameter for engineering applications. In this work the effects of soil characteristics and conditions on the DC soil resistivity are investigated experimentally using remolded soil samples. Several natural silica and artificial glass sands of uniform gradations were tested under variable water resistivity and content, using the two-electrode and the four-electrode soil box methods for dry and wet soil, respectively. The dependence of DC soil resistivity on soil characteristics and conditions, such as grain size, specific surface, pore water conductivity and degree of saturation, is assessed. Soil resistivity decreases with increasing water conductivity and content. It also decreases with decreasing grain size as a result of the shorter current conduction paths (lower tortuosity) and the higher amount of available electrolytes; the contribution of the latter was quantified by measuring the resistivity of several soil:water suspensions. The effects of soil characteristics and conditions on soil resistivity have been well accounted for by considering soil resistivity at saturation as reference. For degree of saturation higher than the percolation threshold soil resistivity is well approximated by Archie's law; parameter values applicable to sandy soil are proposed. A new expression has been derived on a physical basis to describe soil resistivity for degree of saturation values lower than the percolation threshold.

Impact of Electric Field Application During Curing on Epoxy-Carbon Nanotube Nanocomposite Electrical Conductivity

In the present work, the conductivity of multi-walled carbon nanotube (MWCNT) and epoxy resin matrix nanocomposites produced under the action of a 100-V/cm external sinusoidal electric field is studied, for five MWCNT concentration values. The results showed that the AC electrical conductivities of the nanocomposite samples exhibited a large increase compared to those of pure epoxy resin samples. The conductivity at 40 Hz increased from ~ 10−9 S/m for the pure resin samples to 10−2–10−3 S/m for materials with 0.30 wt% MWCNT concentration, while a further increase of up to ~ 10−1 S/m was achieved on the samples produced under the effects of a sinusoidal field. This phenomenon was attributed to a spatial alignment of the MWCNT inside the epoxy matrix and/or the bending of close MWCNT due to the electrostatic force, which created efficient electric current conduction paths along the MWCNT. A proposed new method estimated the value of the current percolation threshold, yielding a result of 0.016 wt% for the sample that was not subjected to the electric field, which then decreased by approximately one order of magnitude for the samples subjected to the electric field.

A dual-trench silicon on insulator high voltage device with an L-shaped source field plate

To improve the breakdown voltage and reduce the specific on-resistance of a small size silicon on insulator (SOI) device, a dual-trench SOI high voltage device with an L-shaped source field plate is proposed. The device has the features as follows: first, a trench gate is adopted. The trench gate widens the current conduction area and makes the current conduction path shorter, thus lowering the specific on-resistance. Second, a SiO2 dielectric layer is introduced into the drift region. This dielectric layer can hold a high electric field, which makes the breakdown voltage greatly increased. Third, an L-shaped source field plate is introduced. This field plate modulates the electric field in the drift region, so increases the optimized doping concentration of the drift region significantly and reduces the specific on-resistance. The results from the two-dimensional semiconductor simulator show that as compared with a conventional SOI device at the same cell pitch, the breakdown voltage is increased by 151%, and the specific on-resistance is reduced by 20%. The specific on-resistance is reduced by 80% at the same breakdown voltage. Compared with a dual-trench SOI device with the same cell pitch, the proposed device maintains the same high breakdown voltage as the dual- trench SOI device, and at the same time, the specific on-resistance is decreased by 26%.

A low on-resistance silicon on insulator lateral double diffused metal oxide semiconductor device with a vertical drain field plate

To reduce the on-resistance and enhance the breakdown voltage of silicon on insulator (SOI) lateral double diffused metal oxide semiconductor (LDMOS) device at the same time, a low on-resistance SOI-LDMOS device with a vertical drain field plate and trench gate and trench drain (VFP-TGTD-SOI-LDMOS) is proposed. The device has the features as follows: first, a trench gate and a trench drain are adopted, which can widen the vertical current conduction area, shorten the lateral current conduction path, and lower the on-resistance. Secondly, a vertical field plate is used, which modulates the electric field around it, reduces the high electric field at the end of the drain electrode, and increases the breakdown voltage. The VFP-TGTD-SOI device is compared with a conventional SOI device, a trench gate SOI device, a trench gate and trench drain SOI device with the same dimensional device parameters using the two-dimensional semiconductor simulator MEDICI. The results show that under the condition of their own highest figure of merit (FOM), the specific on-resistance value of the VFP-TGTD-SOI device is reduced by 53%, 23%, and increased by 87%, respectively and the breakdown voltage is increased by 4% and reduced by 9% and increased by 45%, respectively. By comparing the FOMs of the four structures, it can be seen that the VFP-TGTD-SOI device has the highest FOM, which indicates that among the four structures, it maintains the lower on-resistance and holds the higher breakdown voltage at the same time.

Electrochemical Monitoring of TiO2 Atomic Layer Deposition by Chronoamperometry and Scanning Electrochemical Microscopy

The scanning electrochemical microscope (SECM) was used to characterize the atomic layer deposition (ALD) of TiO2 on indium-doped tin oxide (ITO) substrates by studying electron transfer through pores in the thin films (1− 5n m thickness). The extent of electron transfer, and thus the porosity of the films, was evaluated by transient electrochemistry. These studies show that ALD deposition of TiO2 on ITO does not produce pinhole-free films but rather porous deposits with electrochemical behavior similar to that of microelectrode arrays up to about 30 ALD cycles. All the experimental results are explained in the context of a numerical model developed by finite element analysis and corroborated by complementary conductive atomic force microscopy (cAFM) results that directly reveal localized, nanoscale current conduction paths in thinner TiO2 layers with a transition to more spatially uniform conduction in the thickest layers. SECM images demonstrate the existence of pinholes even on films that have been subjected to more than 100 ALD cycles (thicknesses larger than 4 nm).

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

A novel low specific on-resistance (Ron,sp) silicon-on-insulator (SOI) p-channel lateral double-diffused metal—oxide semiconductor (pLDMOS) compatible with high voltage (HV) n-channel LDMOS (nLDMOS) is proposed. The pLDMOS is built in the N-type SOI layer with a buried P-type layer acting as a current conduction path in the on-state (BP SOI pLDMOS). Its superior compatibility with the HV nLDMOS and low voltage (LV) complementary metal-oxide semiconductor (CMOS) circuitry which are formed on the N-SOI layer can be obtained. In the off-state the P-buried layer built in the N-SOI layer causes multiple depletion and electric field reshaping, leading to an enhanced (reduced) surface field (RESURF) effect. The proposed BP SOI pLDMOS achieves not only an improved breakdown voltage (BV) but also a significantly reduced Ron,sp. The BV of the BP SOI pLDMOS increases to 319 V from 215 V of the conventional SOI pLDMOS at the same half cell pitch of 25 μm, and Ron,sp decreases from 157 mΩ·cm2 to 55 mΩ·cm2. Compared with the PW SOI pLDMOS, the BP SOI pLDMOS also reduces the Ron,sp by 34% with almost the same BV.

Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits

This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$S.S.$</tex></formula> ) and comparable trap-induced <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{T}$</tex></formula> shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm dd})$</tex></formula> , the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way nand, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\sim$</tex></formula> 24%–27% and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\sim$</tex></formula> 13%–15% variations in leakage and delay at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{ \rm dd} = \hbox{0.4}\ \hbox{V}$</tex></formula> , respectively, for the logic circuits evaluated.

Schottky diode with excellent performance for large integration density of crossbar resistive memory

A Schottky diode (SD) with Au/Pt/TiO2/Ti/Pt stacked structure were fabricated for its application to crossbar type resistive switching (RS) memory. The SDs showed a highly promising rectification ratio (∼2.4 × 106 @ ±2 V) between forward and reverse state currents and a high forward current density (∼3 × 105 A/cm2 @ 2 V), which is useful for highly integrated crossbar RS memory. The SD has local forward current conduction paths, which provides extremely scaled devices with an advantage. The minimization of interconnection line resistance is also important to provide sufficient current to achieve stable operation of RS memory.