Current Aperture Vertical Electron Transistor Research Articles

The optimization of a GaN-based current aperture vertical electron transistor

The main objective of this paper is to simulate and optimize a current aperture vertical electron transistor (CAVET) based on gallium nitride (GaN), which combines both a two-dimensional electron gas (2DEG) and a vertical structure using the SILVACO-TCAD simulator. The dimensions of the structure were reduced by 45% to minimize the size and improve the performances of the proposed device; also, a part of aluminum nitride (AlN)was added to the current blocking layer (CBL) to modulate the conduction band profile. The results obtained from the simulation of our structure demonstrated a maximum drain current of 1.8 A/mm, Pinch-off voltage (VP) of -6 V, drain induced barrier lowering (DIBL) of 166 mV/V, maximum transconductance (gm) of 570 mS/mm, gate-leakage of 7.10-7 A, cut-off frequency (ft) of 200 GHz, maximum oscillation frequency (fMax) of 400 GHz. The proposed device exhibited outstanding performance while consuming low power, making it well-suited for use as a low-noise amplifier (LNA) in satellite reception applications.

Novel high-voltage GaN CAVET with high threshold voltage and low reverse conduction loss

A novel GaN current-aperture vertical electron transistor (CAVET) with an energy band pinning (EBP) structure (EBP-CAVET) is proposed and investigated by simulations. The EBP-CAVET is featured with hybrid contacts on the p-GaN layer, locally having Ohmic contact combined with Schottky gate metals in the longitudinal direction. The Ohmic contact is shorted to the source electrode and the Schottky gate metals are shorted to the gate electrode. The conduction band (Ec) in the gate region is modulated by the alternately arranged contacts. In the Ohmic contact region, Ec remains a fixed value, which acts as an energy band pinning and suppresses the variation of the Ec in the gate region. In the on-state (VGS > 0 V) and blocking-state with high VDS, the EBP structure inhibits the Ec shifting downwards in the gate region to achieve a high threshold voltage (Vth), a low leakage current density (Jdss), and a high breakdown voltage (BV). In the reverse conduction state (VDS < 0 V &VGS ≤ 0 V), the EBP structure suppresses the Ec shifting upwards to achieve a low and independent of gate bias reverse turn-on voltage (VRT). The proposed EBP-CAVET achieves a high Vth of 2.10 V, a VRT of 0.69 V, a low Jdss of 3.1 × 10−11 A/cm2 at VDS = 1000 V, a high BV of 1660 V. Compared with an integrated Schottky barrier diode or fin diode in a field effect transistor (FET), the EBP structure occupies a much smaller chip area. Thus, the EBP-CAVET achieves a low specific ON-resistance (Ron,sp) of 1.19 mΩ cm2 and an extremely high power-figure-of-merit (PFOM) up to 2.32 GW/cm2. Consequently, the proposed structure presents a new design concept and enhances the application potential for GaN CAVET with high Vth and low reverse conduction loss.

Improvement of reverse conduction characteristic and single event effect for a novel vertical GaN field effect transistor with an integrated MOS-channel diode

A vertical GaN-based field-effect transistor with an integrated MOS-channel diode (MCD) is used to improve the reverse conduction characteristic and transient single-event effect (SEE). The device features an MCD acting as a free-wheel diode formed between trench source metal on the source dielectric and a P-type blocking layer (PBL), wherein MIS structure is formed by trench source, source dielectric and N-drift. At the reverse conduction (VSD > 0 V, VGS ≤ 0 V), because the channel between the PBL and the MIS structure is opened, the MCD turns on to realize a low reverse turn-on voltage (VRT) and the VRT is independent of VGS. At the forward conduction (VDS > 0, VGS > Vth), the MCD is pinched-off without influencing the on-state characteristic of the MCD-FET. Moreover, owing to the modulation effect of the PBL on electric-field distribution, both the impact ionization rate and transient SEE peak current (Ipeak) is reduced. Consequently, a low VRT = 0.67 V, low Ipeak = 10.11 mA and high BV = 1573 V are achieved. The VRT and Ipeak are decreased by 46.4 % and 64.9 %, respectively, compared with those of the conventional current aperture vertical electron transistor (CAVET).

Improved GaN-based Current Aperture Vertical Electron Transistor (CAVET)

The objectives of this research are to improve and optimize a vertically structure HEMT device based on AlGaN/GaN heterojunctions. This novel proposed structure with double gate command would allow for a better dispersion of the electric field, with peaks lower and farther from the surface than a lateral structure. The research focuses on estimating the performance of a GaN-based vertical structure called a "Current Aperture Vertical Electron Transistor (CAVET)" that combines a two-dimensional electron gas (2DEG) and a vertical structure with technology, operation, settings, and performance that can be seen in power applications. Performance operating at high frequencies and low power loss consumer, a device that will, therefore, lead function to best in electrical power and higher system efficiency with IDss equal 0.95 A, -6 V for pinch-off, fT/fMax are 110/250 GHz and 14 % for Drain-lag.

Comparative Performance Evaluation for 1.2–10kV Conventional and Superjunction GaN Current Aperture Vertical Electron Transistors

The performance potentials and limits for GaN current aperture vertical electron transistors with conventional, doped, and natural polarization superjunction (PSJ) drift layers at 1.2–10 kV breakdown voltage (BV) ratings are quantitatively compared. The static and dynamic performance parameters for each device are simulated and extracted. The specific on‐resistance RON,sp and specific total charge QT,sp (defined as the sum of specific gate charge QG,sp and specific drain–source charge QDS,sp) are extracted from Medici technology computer‐aided design simulations representing both the static and dynamic performance respectively. Moreover, a developed figure‐of‐merit (FoM) (RON,sp · QT,sp) is used to quantitively compare the performance of these field‐effect transistors in the range of BV ratings. Compared to the doped superjunction (DSJ) and conventional CAVETs, natural PSJ CAVET exhibits 1%–60% and 70%–99% reduction in RON,sp, while it is 100 to 1000× reduction in QT,sp, at BV between 1.2 and 10 kV respectively. Simultaneously, 22%–80% and 80%–99% reduction in performance FoM respectively are found.

High Current Density Trench CAVET on Bulk GaN Substrates with Low-Temperature GaN Suppressing Mg Diffusion

We report that, for the first time, a low-temperature GaN (LT-GaN) layer prepared by metal–organic chemical vapor deposition (MOCVD) regrowth was used as a Mg stopping layer (MSL) for a GaN trench current–aperture vertical electron transistor (CAVET) with p-GaN as a carrier blocking layer (CBL). Inserting LT-GaN on top of the p-GaN effectively suppresses Mg out-diffusion into the regrown AlGaN/GaN channel, contributing to the high current capability of GaN vertical devices with a p-GaN CBL. With different MOCVD growth conditions, MSLs inserted in trench CAVETs were comprehensively investigated for the influence of MSL regrowth temperature and thickness on device performance. With the best on-state current performance obtained in this study, the trench CAVET with a 100 nm thick MSL regrown at 750 °C shows a high drain current of 3.2 kA/cm2 and a low on-state resistance of 1.2 mΩ∙cm2. The secondary ion mass spectrometry (SIMS) depth profiles show that the trench CAVET with the 100 nm thick MSL regrown at 750 °C has a dramatically decreased Mg diffusion decay rate (~39 nm/decade) in AlGaN/GaN channel, compared to that of the CAVET without a MSL (~104 nm/decade). In developing GaN vertical devices embedded with a Mg-doped p-type layer, the LT-GaN as the MSL demonstrates a promising approach to effectively isolate Mg from the subsequently grown layers.

Design of the GaN based CAVET with SiO2–InGaN hybrid current blocking layer

The emergence of vertical GaN devices solves the problem of insufficient voltage withstand capacity of horizontal GaN devices. However, the current output capability of vertical GaN devices is not comparable to that of lateral GaN devices. So we propose a Al0.3Ga0.7N/GaN current-aperture vertical electron transistor with a SiO2–In0.05Ga0.95N hybrid current-blocking layer (CBL). Through simulation and in-depth study of the proposed device, the results show that the GaN/InGaN secondary channel enhances the saturation output current of the device, achieving a saturated output current (I DSS) of 985 mA mm−1 and a transconductance (G m) of 256 mS mm−1, which are 30% and 25% higher than that of the single-channel SiO2 CBL device, respectively. The breakdown voltage is 230 V and the on-resistance (R on) is only 0.58 mΩ cm2.

Noise characterisation of GaN current aperture vertical electron transistor metal‐insulated semiconductor field effect transistor with Δ‐shaped gate for low noise radio frequency amplifiers

In this article, vertical CAVET with boron-doped GaN layer as current blocking layer (CBL) for AlGaN/GaN is proposed in this study, and different electrical characteristics of the devices, such as DC (Ids − Vds), small-signal radio frequency and high-frequency microwave noise performances, are characterised using Synopsys TCAD simulations. The vertical CAVET AlGaN/GaN metal-insulated semiconductor field effect transistor (MIS-HEMT) has been found to have a high threshold VT = 6.36 V, drain saturation current, Ids,sat = 3.41 kA/cm2, reduced OFF-state current <10−12 and improved high frequency and noise performances. The findings provide insight on noise sources and provide information on how to improve GaN transistor noise performance. Its useful characterisation tool for learning more about the imperfections in advanced AlGaN/GaN MIS-HEMTs and how they evolve. A two-port noise equivalent-circuit description is used to calculate data for noise. Using data from noise and scattering parameters that have been measured, we evaluated the effect of noise sources due to gate and drain, as well as their correlation. The devices exhibit a minimum noise figure (NFmin) and an equivalent noise resistance (Rn) of 1.21 dB and 20 Ω at 20 GHz, with Vgs = 5 V and Vds = 10 V, which is small and appropriate for low-noise amplifiers with a wide bandwidth. The maximum output power density Pout of 23 dBm and the maximum PAE of 63.3% are achieved for GaN V-shaped CAVET MIS-HEMTs with Vds = 10 V at 3.12 GHz is achieved. A comparison is made between the noise performance of conventional HEMTs, MIS-HEMTs and FETs. The methods for obtaining the noise figure (NFmin) and other noise metrics are then explained and compared with those found in the literature.

Study of High-Performance GaN-Based Trench CAVET with Stepped Doping Microstructure.

In this article, an innovative GaN-based trench current-aperture vertical electron transistor (CAVET) with a stepped doping microstructure is proposed and studied using Silvaco-ATLAS. According to the simulation and analyzed characteristics, the best performance renders a remarkable Baliga’s figure of merit (FOM) of 4.767 GW·cm2 owing to the modulation of the electric-field distribution. By adjusting the size of the stepped doping microstructure and doping concentration in the GaN drift, the maximum optimized result can achieve a relatively high breakdown voltage (BV) of 2523 V with a very low specific on-resistance (Ron,sp) of 1.34 mΩ·cm2, or the BV can be improved to 3024 V with a specific on-resistance (Ron,sp) of 2.08 mΩ·cm2. Compared with the conventional superjunction GaN-based trench CAVET, the newly demonstrated structure can achieve a 43% reduction in Ron,sp and increase by almost 20% the original BV. These results indicate the superiority of using the stepped doping microstructure in a trench CAVET to improve the BV and decrease Ron,sp, providing a reference for further development of GaN-based CAVETs.

(Invited) Breakthrough Avalanche and Short Circuit Robustness in Vertical GaN Power Devices

After decades of relentless efforts, GaN power devices, specifically, the lateral GaN high-electron mobility transistor (HEMT), have been commercialized in the 15-650 V classes. Owing to GaN’s competitive physical properties over Si and SiC for power electronics, GaN HEMTs allow for higher switching frequency and therefore, have already seen wide adoptions in fast chargers, wireless charging, data centers, and electrified transportation. Despite the success of lateral GaN HEMTs, a vertical device structure is usually believed to be more favorable for high-voltage, high-power devices. In the last few years, with the advent and maturity of large-diameter, low-dislocation GaN wafers on freestanding GaN substrates, a new generation of vertical GaN power devices have been developed to extend GaN’s application space beyond 650 V. Very recently, several industrial vertical GaN devices in the voltage classes of 1.2-1.7 kV have been demonstrated, which are close to commercialization.This presentation will review the key advancements in vertical GaN power devices in the past decade, with a focus on the device technologies that are being commercialized, and provide a prospective for research and development in the next decade. The devices to be covered will include two-terminal power rectifiers including the p-n diodes, Schottky barrier diodes, junction barrier Schottky diodes, and trench MIS/MOS barrier Schottky diodes. The transistors will include the trench and planar MOSFETs, current-aperture vertical electron transistors, fin-channel MOSFETs, and fin-channel JFETs. Particular emphasis will be on large-area rectifiers and transistors with a device performance superior to similarly-rated Si and SiC transistors. The newly demonstrated avalanche and short-circuit robustness in vertical GaN devices, which are lacking in lateral GaN HEMTs, as well as their underlying device physics, will also be introduced. The presentation will be concluded by a discussion of current challenges and future application spaces of vertical GaN devices, as well as emerging vertical GaN devices (e.g., superjunction) under development.

On the origin of the turn-on voltage drop of GaN-based current aperture vertical electron transistors

Non-linear output characteristics and the related turn-on voltages of GaN-based current aperture vertical electron transistors (CAVETs) are investigated experimentally. The resistive components are systematically analyzed in dependence of the device layout to determine the dominant resistances in the devices. Current–voltage (IV) and capacitance–voltage-characteristics (CV) are compared to a proposed planar-doped barrier diode (PDBD) model, and the influence of the bound sheet charge density and drift layer carrier concentration is discussed. The observed CV characteristics are in contrast to the PDBD model as a clearly voltage-dependent capacitance was observed and dopant-diffusion forming a p-type aperture was ruled out. Thermionic emission was verified by temperature-dependent IV characteristics indicating interface states causing a potential barrier. Transient drain current measurements revealed a single dominating trap level with an activation energy of EA = 1.086 ± 0.015 eV. This activation energy was attributed to carbon-related acceptor states present at the regrowth interface and the drift layer. Additional test structures revealed that the interface potential barrier and the space charge in the drift layer limit the initial charge transport causing a turn-on voltage in the devices. The results point out the significance of a precise control of the regrowth interface properties and the effective carrier density in the drift layer to enable efficient, high-power devices based on the CAVET technology.

Thermal Management of β-Ga₂O₃ Current Aperture Vertical Electron Transistors

Beta-gallium oxide ( β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) has attracted considerable attention for power devices due to its superior properties and the availability of device-quality native substrates compared to gallium nitride (GaN) technologies. In particular, devices such as the current aperture vertical electron transistor (CAVET) have a higher breakdown voltage compared to lateral transistors made from β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> . However, because of the low thermal conductivity of β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , thermal management strategies at the device level are required in order to achieve high power operation. Here, we present a thermal modeling study of CAVET power transistors and analyze the impact of thermal management strategies on their thermal performance. Among the various cooling strategies, double-side cooling has the largest impact on device cooling. Double-side cooling in combination with a heat spreader can suppress the device's thermal resistance from 24.5 to 4.86 mm · <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C/W, allowing for a high-power-density CAVET device. The modeling and analysis results presented in this work can be utilized as a guide for improvement of the vertical β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> device performance for future power electronics applications.

Vertical GaN Power Devices: Device Principles and Fabrication Technologies—Part II

Vertical gallium nitride (GaN) power devices are enabling next-generation power electronic devices and systems with higher energy efficiency, higher power density, faster switching, and smaller form factor. In Part I of this review, we have reviewed the basic design principles and physics of building blocks of vertical GaN power devices, i.e., Schottky barrier diodes and p-n diodes. Key topics such as materials engineering, device engineering, avalanche breakdown, and leakage mechanisms are discussed. In Part II of this review, several more advanced power rectifiers are discussed, including junction barrier Schottky (JBS) rectifiers, merged p-n/Schottky (MPS) rectifiers, and trench metal-insulator-semiconductor barrier Schottky (TMBS) rectifiers. Normally- OFF GaN power transistors have been realized in various advanced device structures, including current aperture vertical electron transistors (CAVETs), junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and fin field-effect transistors (FinFETs). A detailed analysis on their performance metrics is provided, with special emphasis on the impacts of key fabrication processes such as etching, ion implantation, and surface treatment. Lastly, exciting progress has been made on selective area doping and regrowth, a critical process for the fabrication of vertical GaN power devices. Various materials characterization techniques and surface treatments have proven to be beneficial in aiding this rapid development. This timely and comprehensive review summarizes the current progress, understanding, and challenges in vertical GaN power devices, which can serve as not only a gateway for those interested in the field but also a critical reference for researchers in the wide bandgap semiconductor and power electronics community.

Metal organic chemical vapour deposition regrown large area GaN‐on‐GaN current aperture vertical electron transistors with high current capability

Metal organic chemical vapour deposition regrown large area GaN‐on‐GaN current aperture vertical electron transistors with high current capability

Growth and Fabrication of Quasivertical Current Aperture Vertical Electron Transistor Structures

The current aperture vertical electron transistor (CAVET) combines the high carrier mobility of the AlGaN/GaN heterostructure with the better electric field distribution of the vertical topology, allowing for higher power densities if compared with lateral high electron mobility transistors (HEMTs). The formation of a current blocking layer (CBL), without degenerating the aperture region and the subsequently overgrown AlGaN/GaN heterostructure is the key building block of such devices. Herein, a comparison of GaN:Mg nonplanar selective area growth (SAG) and Mg‐ion implantation is carried out primarily focusing on structural evolution, Mg distribution, and 2D electron gas (2DEG) performance. The epitaxial growth process in SAG is correlated to local growth increase and ridge development, and then optimized regarding mesa filling. AlGaN/GaN regrowth is analyzed regarding structural evolution after overgrowth and Mg distribution into the GaN channel. Considerably lower Mg‐distribution into subsequently grown layers is detected for implanted samples in agreement with the electrical performance of the overgrown AlGaN/GaN heterostructures. A GaN‐on‐Si quasivertical CAVET structure with an Mg‐implanted CBL and 250 nm channel thickness is fabricated. High surface quality and proper 2DEG performance demonstrate the potential use of GaN‐on‐Si CAVET's using Mg implantation for CBL fabrication.

Effect of U-shape trench etching process on electrical properties of GaN vertical trench metal-oxide-semiconductor field-effect transistor

As reported by several market analysts, GaN-based power devices show great potential applications in the low and medium voltage range ( &lt; 900 V). For high voltage ( &gt; 1200 V), including ship transportation and power grid, the future applications of GaN highly depend on the development of vertical devices based on GaN substrates. Several vertical devices have been reported, such as current aperture vertical electron transistors (CAVETs), U-shape trench metal-oxide-semiconductor field-effect transistors (UMOSFETs), and fin power transistors. And the UMOSFETs show potential advantages due to greater simplicity in material epitaxy and fabrication process. In the fabrication of UMOSFETs, the U-shape trench dry etching is the most critical process. The GaN sidewalls after dry etching directly affect the interface state characteristics in the MOS structure and the channel electron transport. In this work, etching optimization including etching radio-frequency (RF) power and etching mask is investigated and process-dependent electrical characteristics of GaN UMOSFETs are also studied. The appropriate decrease of RF power ensuring the steep sidewalls can effectively improve the channel electron mobility from 35.7 cm&lt;sup&gt;2&lt;/sup&gt;/(V·s) to 48.1 cm&lt;sup&gt;2&lt;/sup&gt;/(V·s) and consequently increase the ON-state current and reduce the ON-state resistance. Larger etching damage to the p-GaN sidewall caused by higher RF power leads the scattering effects to increase and the mobility of the channel carriers to decrease. The interface state density at the channel can be extracted by the subthreshold swing. The interface state density decreases to 1.90 × 10&lt;sup&gt;12&lt;/sup&gt; cm&lt;sup&gt;–&lt;/sup&gt;&lt;sup&gt;2&lt;/sup&gt;·eV&lt;sup&gt;–1&lt;/sup&gt; when the RF power is regulated to 50 W, which is only half of the interface state density when RF power is 135 W. Similar breakdown voltages (350－380 V) are measured for these devices with varying RF power, which are governed by gate early breakdown. Positive valence band offset is formed in the SiO&lt;sub&gt;2&lt;/sub&gt;/GaN MOS structure and the early breakdown occurs due to the holes accumulating at the SiO&lt;sub&gt;2&lt;/sub&gt;/GaN interface. The etching uniformity at the bottom of U-shape trench can be improved by using the SiO&lt;sub&gt;2&lt;/sub&gt; hard masks instead of photoresist masks. Sub-trenches at both ends of the trench bottom are observed in the device with photoresist masks, leading the carrier scattering to increase and ON-state current to decrease. Besides, the interface state density decreases from 3.42 × 10&lt;sup&gt;12&lt;/sup&gt; cm&lt;sup&gt;–2&lt;/sup&gt;·eV&lt;sup&gt;–1&lt;/sup&gt; to 2.46 × 10&lt;sup&gt;12&lt;/sup&gt; cm&lt;sup&gt;–2&lt;/sup&gt;·eV&lt;sup&gt;–1&lt;/sup&gt; with a SiO&lt;sub&gt;2&lt;/sub&gt; hard mask layer used. Compared with 1.6 μm photoresist mask, the thinner SiO&lt;sub&gt;2&lt;/sub&gt; mask with a thickness of 500 nm has a small sidewall area, which weakens the high-energy ion reflection in the inductively coupled plasma system. Consequently, the over-etching at the bottom ends of the trench is improved significantly and therefore the fabricated GaN UMOSFET has higher channel mobility and a lower interface state density.

Metalorganic vapour-phase epitaxy of AlGaN/GaN heterostructures on chlorine plasma etched GaN templates without buried conductive layer

In this work we present approach that allows regrowth of AlGaN/GaN heterostructures on plasma etched GaN templates without occurrence of buried conductive layer. Discussion about the influence of RIE (reactive ion etching) process on the properties of GaN surface is followed by presentation of experimental work results focused on reconstruction of GaN template surface after etching in chlorine plasma in order to growth AlGaN/GaN heterostructure without parasitic channel. Analysis of GaN surface treatment after RIE process using 10% aqueus HF solution and low temperature GaN (LT-GaN) nucleation layer is carried out, including SEM (scanning electron microscopy) imaging and SIMS (secondary ion mass spectroscopy) profiling. The AlGaN/GaN heterostructures with the thickness as low as 250 nm deposited on plasma etched GaN templates with sheet resistance under 600 Ω/□ and good uniformity were fabricated using this approach. Presented method can be used in fabrication of current aperture vertical electron transistor (CAVET) structures with low leakage currents.

Design and Simulation of GaN Superjunction Transistors With 2-DEG Channels and Fin Channels

High-performance 2-D-electron-gas (2-DEG) channel and submicron fin-shaped channel have recently been demonstrated in vertical GaN power transistors. This indicates that, unlike Si and SiC, the inversion-type metal–oxide–semiconductor channel is no longer the “default option” for future GaN superjunction transistors. This paper demonstrates the design and simulation of GaN superjunction transistors with 2-DEG and fin channels, i.e., a superjunction current-aperture vertical electron transistor (SJ-CAVET) and a superjunction fin field-effect-transistor (SJ-FinFET). A breakdown voltage over 2.2 kV and a specific on-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\mathrm{\scriptscriptstyle ON},\mathrm {sp}}$ </tex-math></inline-formula> ) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.35~\text {m}\Omega \cdot \text {cm}^{2}$ </tex-math></inline-formula> were demonstrated in the simulated GaN SJ-CAVETs and SJ-FinFETs with 10- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thick superjunction region. Mixed-mode simulations were used to evaluate their performance in 1.7 kV, 50-A power switching applications. Their <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\mathrm{\scriptscriptstyle ON},\mathrm {sp}}$ </tex-math></inline-formula> and die size are at least 30-to-50-fold smaller than that of today’s best 1.7-kV power transistors. Thanks to the smaller die size, the junction capacitances and switching charges are significantly smaller, allowing for a megahertz practical switching frequency which is at least tenfold higher than today’s 1.7-kV power transistors. The simulations of higher voltage GaN SJ-CAVETs and SJ-FinFETs up to 10 kV reveal consistent advantages over commercial transistors. These results show the great potentials of GaN SJ-CAVETs and SJ-FinFETs for future medium-voltage high-frequency power applications.

A normally OFF GaN CAVET and its thermal and trap analysis

We propose and investigate an enhancement-mode (normally OFF) current-aperture vertical electron transistor (CAVET) with a novel structure. The novelty lies in the achievement of the desired normally OFF/enhancement-mode operation through polarization engineering by employing a hybrid current-blocking layer (HCBL) made of an isolation material and aluminum nitride (AlN). The AlN introduces a conduction barrier for the electron gas located at the AlGaN–GaN interface, effectively making the proposed device operate in an enhancement/normally OFF mode. The isolation portion of the HCBL suppresses the off-state leakage current and drastically improves the breakdown performance. Calibrated technology computer-aided design (TCAD) simulations show that the proposed polarization-engineered (PE)-CAVET structure displays normally OFF operation with a threshold voltage (VTH) of 2.2 V and a breakdown voltage twice that of the conventional GaN CAVET. A study of the thermal properties of the proposed structure reveals a significant improvement in the drain current due to the use of a heat sink, while the trap analysis shows that the leakage current in the CAVET structure can be suppressed by carefully choosing a proper acceptor trap concentration and energy level. On the other hand, donor traps degrade the performance of the CAVET, albeit not as severely as in the conventional device.

A Demonstration of Nitrogen Polar Gallium Nitride Current Aperture Vertical Electron Transistor

We report the first demonstration of Nitrogen polar (N-polar) GaN current aperture vertical electron transistor with a blocking electric field over 2.9 MV/cm. The devices were grown by metalorganic chemical vapor deposition on a c-plane sapphire substrate. The fabrication involved a maskless planar regrowth of a very thin-AlN layer above the current blocking layer, which induced a two-dimensional electron gas (2DEG) in the channel, and also prevented the out-diffusion of activated Mg ions into the GaN channel layer. The alloyed source and drain ohmic contacts on the regrown n+-GaN layer offered the low-contact resistance of 0.18 $\text{m}\Omega \cdot \text {cm}^{2}$ ( $0.22~\Omega \cdot \text {mm}$ ). The device displayed a maximum drain current of 1.68kA/cm2 with a low RON, SP of 2.48 $\text{m}\Omega \cdot \text {cm}^{2}$ . With just about 200 nm drift layer, a three-terminal breakdown voltage of 58 V was achieved. The output characteristics were free of dispersion under pulsed measurements with $80~\mu \text{s}$ and 500 ns pulse widths. The N-polar current aperture vertical electron transistors show fundamentally significant advantages in favor of using Mg2+-implanted GaN as current blocking layers compared with Ga-polar counterparts.