Effect of U-shape trench etching process on electrical properties of GaN vertical trench metal-oxide-semiconductor field-effect transistor

Abstract

As reported by several market analysts, GaN-based power devices show great potential applications in the low and medium voltage range ( < 900 V). For high voltage ( > 1200 V), including ship transportation and power grid, the future applications of GaN highly depend on the development of vertical devices based on GaN substrates. Several vertical devices have been reported, such as current aperture vertical electron transistors (CAVETs), U-shape trench metal-oxide-semiconductor field-effect transistors (UMOSFETs), and fin power transistors. And the UMOSFETs show potential advantages due to greater simplicity in material epitaxy and fabrication process. In the fabrication of UMOSFETs, the U-shape trench dry etching is the most critical process. The GaN sidewalls after dry etching directly affect the interface state characteristics in the MOS structure and the channel electron transport. In this work, etching optimization including etching radio-frequency (RF) power and etching mask is investigated and process-dependent electrical characteristics of GaN UMOSFETs are also studied. The appropriate decrease of RF power ensuring the steep sidewalls can effectively improve the channel electron mobility from 35.7 cm<sup>2</sup>/(V·s) to 48.1 cm<sup>2</sup>/(V·s) and consequently increase the ON-state current and reduce the ON-state resistance. Larger etching damage to the p-GaN sidewall caused by higher RF power leads the scattering effects to increase and the mobility of the channel carriers to decrease. The interface state density at the channel can be extracted by the subthreshold swing. The interface state density decreases to 1.90 × 10<sup>12</sup> cm<sup>–</sup><sup>2</sup>·eV<sup>–1</sup> when the RF power is regulated to 50 W, which is only half of the interface state density when RF power is 135 W. Similar breakdown voltages (350－380 V) are measured for these devices with varying RF power, which are governed by gate early breakdown. Positive valence band offset is formed in the SiO<sub>2</sub>/GaN MOS structure and the early breakdown occurs due to the holes accumulating at the SiO<sub>2</sub>/GaN interface. The etching uniformity at the bottom of U-shape trench can be improved by using the SiO<sub>2</sub> hard masks instead of photoresist masks. Sub-trenches at both ends of the trench bottom are observed in the device with photoresist masks, leading the carrier scattering to increase and ON-state current to decrease. Besides, the interface state density decreases from 3.42 × 10<sup>12</sup> cm<sup>–2</sup>·eV<sup>–1</sup> to 2.46 × 10<sup>12</sup> cm<sup>–2</sup>·eV<sup>–1</sup> with a SiO<sub>2</sub> hard mask layer used. Compared with 1.6 μm photoresist mask, the thinner SiO<sub>2</sub> mask with a thickness of 500 nm has a small sidewall area, which weakens the high-energy ion reflection in the inductively coupled plasma system. Consequently, the over-etching at the bottom ends of the trench is improved significantly and therefore the fabricated GaN UMOSFET has higher channel mobility and a lower interface state density.