Abstract

Beta-gallium oxide ( β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) has attracted considerable attention for power devices due to its superior properties and the availability of device-quality native substrates compared to gallium nitride (GaN) technologies. In particular, devices such as the current aperture vertical electron transistor (CAVET) have a higher breakdown voltage compared to lateral transistors made from β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> . However, because of the low thermal conductivity of β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , thermal management strategies at the device level are required in order to achieve high power operation. Here, we present a thermal modeling study of CAVET power transistors and analyze the impact of thermal management strategies on their thermal performance. Among the various cooling strategies, double-side cooling has the largest impact on device cooling. Double-side cooling in combination with a heat spreader can suppress the device's thermal resistance from 24.5 to 4.86 mm · <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C/W, allowing for a high-power-density CAVET device. The modeling and analysis results presented in this work can be utilized as a guide for improvement of the vertical β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> device performance for future power electronics applications.

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