Cross-point Memory Research Articles

Solution‐Processed Flexible Threshold Switch Devices

AbstractFlexible threshold switch devices are essential for low‐power and high‐speed semiconductor devices. Especially, bidirectional threshold switch has been regarded as the ideal switching device for ultrahigh‐density crosspoint memory devices. Here, a flexible Pt/Ag‐doped ZnO/Pt switch on the flexible plastic substrate synthesized by electrochemical bottom‐up deposition is introduced. The flexible switch has bidirectional threshold switching behavior with ultralow off‐current, high selectivity (≈107), and super‐steep threshold slope. The bidirectional threshold switching behavior is related to migration of silver ions to form Ag filament. This device shows stable electrical properties, endures constant voltage stress, and retains good reliability under mechanical stress. It is believed that this study would open up new possibilities for high‐density flexible memory devices by introducing flexible novel bidirectional, high‐performance switching devices for emerging flexible electronics.

Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays

Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo (MC) compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With MC SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependence on device uniformity and supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ), and the array bias scheme is a key knob. Lowering array V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random access simulations indicate that data sparsity statistically benefit write functionality and energy consumption. Finally, we show that a pseudo-subarray topology with uniformly distributed preforming cells in the pristine high-resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance.

Electrode effect regulated resistance switching and selector characteristics in Nb doped SrTiO3 single crystal for potential cross-point memory applications

Current-voltage characteristics of Nb doped SrTiO3 single crystals are detected at room temperatures. Results reveal that modifications of electrode configurations play a significant role on current-voltage behaviors. The asymmetric selector characteristics and symmetrical selector behaviors are the first reported in Nb doped SrTiO3 single crystals, which can be controlled by changing electrode configurations. A new model of Ag nanofilament can explain selector characteristics. Ohmic and space charge limited current mechanisms controlled typical resistance switching behaviors with good cyclic properties are also observed. Schottky barrier electrical conduction mechanism related typical diode behaviors are observed, while voltage is applied on same top electrodes Au.

Cross-point memory design challenges and survey of selector device characteristics

In this survey, the design challenges of cross-point memory arrays with emerging nonvolatile memory technologies are discussed. In particular, the write/read scheme for cross-point memory and the a...

A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System

In this paper, we study the 1-selector1-resistor (1S1R) cross-point resistive random access memory (ReRAM) array because of its high density, fast access time, and ultralow stand-by power. Specifically, we focus on an access scheme where a data line is parallelly accessed from multiple subarrays with multibits accessed per subarray. A direct implementation of such a scheme has high energy efficiency but lower reliability compared with a single bit per subarray baseline scheme. So this paper proposes a low cost multilayer approach to improve energy-efficiency of multibits per access scheme without compromising reliability. At the cell level, we show how proper choices of bit-line and source-line voltage and SET recovery help reduce error rate by ten times. At the system level, we propose a new rotated multiarray access scheme where the average error rate of every accessed data line is one order of magnitude lower than the worst case, making it possible to achieve block failure rate of 10-10 with a simple Bose, Chaudhuri, and Hocquenghem t = 4 code. We show that for a 1 GB 1S1R ReRAM, the proposed approach can reduce energy by 41% with 2% extra area while maintaining latency and reliability compared with the baseline system.

Cross-Point Resistive Switching Memory and Urea Sensing by Using Annealed GdOx Film in IrOx/GdOx/W Structure for Biomedical Applications

Resistive switching characteristics and urea sensing have been investigated by using annealed GdOx film in IrOx/GdOx/W cross-point memory for the first time. The annealed GdOx film shows larger polycrystalline grains as compared to as-deposited films, which is observed by high-resolution transmission electron microscope (HRTEM) and X-ray diffraction patterns (XRD). Surface roughness of the GdOx films on W nano-dome is observed by atomic force microscope (AFM). The annealed IrOx/GdOx/W cross-point memory shows resistance ratio of 1000× times higher, multi-level operation with varying current compliance (CC) from 10–300 μA, good non-linearity factor of 8.3, good dc switching cycles of > 1000 at CC of 10 μA, long read endurance of >109 cycles with pulse width of 1 μs at higher read voltage of −0.5 V, and high speed operation of 100 ns. Repeatable resistive switching characteristics at low CC of 10 μA and mechanism are due to the electric field enhancement on the W nano-dome simulated by MATLAB, which controls the O2− ions migration through polycrystalline GdOx grain boundary as well as Schottky barrier height modulation (0.59 vs. 0.39 eV). In addition, the annealed GdOx membrane in electrolyte-insulator-semiconductor (EIS) structure shows higher pH sensitivity than the as-deposited film (53.2 vs. 45.1 mV/pH) and lower drift (1.8 vs. 2.6 mV/hr) as well as lower detection of pH change (0.034). Detection of pH and urea sensing from 6 to 24 mg/dl have been measured by using cross-point memory, and the sensing mechanism is also discussed, which will be very useful for real healthcare unit in near future.

A Fast and Reliable Cross-Point Three-State/Cell ReRAM

We present a fast and reliable fully integrated cross-point three-state cell resistive random access memory. We accomplish swift back-and-forth hopping among the three resistance states by current-limiting set and in situ bit line regulating reset writing. The self-stuffing word line driver alleviates resistance variations in medium and low resistance states by 2.3 times and 3 times, respectively. The proprietary analog-to-digital converter type transimpedance sense amplifier achieves fast and reliable multilevel read. We integrated a 16-kbit cross-point array and periphery circuits using 350-nm CMOS technology.

Scalable cross-point resistive switching memory and mechanism through an understanding of H2O2/glucose sensing using an IrOx/Al2O3/W structure.

The resistive switching characteristics of a scalable IrOx/Al2O3/W cross-point structure and its mechanism for pH/H2O2 sensing along with glucose detection have been investigated for the first time. Porous IrOx and Ir3+/Ir4+ oxidation states are observed via high-resolution transmission electron microscope, field-emission scanning electron spectroscopy, and X-ray photo-electron spectroscopy. The 20 nm-thick IrOx devices in sidewall contact show consecutive long dc cycles at a low current compliance (CC) of 10 μA, multi-level operation with CC varying from 10 μA to 100 μA, and long program/erase endurance of >109 cycles with 100 ns pulse width. IrOx with a thickness of 2 nm in the IrOx/Al2O3/SiO2/p-Si structure has shown super-Nernstian pH sensitivity of 115 mV per pH, and detection of H2O2 over the range of 1-100 nM is also achieved owing to the porous and reduction-oxidation (redox) characteristics of the IrOx membrane, whereas a pure Al2O3/SiO2 membrane does not show H2O2 sensing. A simulation based on Schottky, hopping, and Fowler-Nordheim tunneling conduction, and a redox reaction, is proposed. The experimental I-V curve matches very well with simulation. The resistive switching mechanism is owing to O2- ion migration, and the redox reaction of Ir3+/Ir4+ at the IrOx/Al2O3 interface through H2O2 sensing as well as Schottky barrier height modulation is responsible. Glucose at a low concentration of 10 pM is detected using a completely new process in the IrOx/Al2O3/W cross-point structure. Therefore, this cross-point memory shows a method for low cost, scalable, memory with low current, multi-level operation, which will be useful for future highly dense three-dimensional (3D) memory and as a bio-sensor for the future diagnosis of human diseases.

Analysis of Functional Oxide based Selectors for Cross-Point Memories

We present an extensive analysis of functional-oxide based selector devices for cross-point memories from the perspectives of materials through arrays. We describe the design constraints required for proper functionality of a cross-point array and translate these constraints to figures of merit for the selector materials. The proposed figures of merit, related to the resistivities of the functional oxide in the metallic and insulating states and the critical current densities for insulator-metal transitions, determine whether or not a functional oxide is suitable to be employed as a selector for a memory technology. Our analysis shows the importance of co-optimizing the selector length with the read/write voltages and establishes the range of these parameters for proper functionality. We also perform an extensive material space analysis for the selector, relating the selector properties to the achievable array metrics. For instance, we show that optimized memory array with single crystal VO $_{\mathrm {{2}}}$ based selector and spin-memory element achieves $\sim 25\mu \text {A}$ sense margin with ~ 30% read disturb margin and 40ns write time. The leakage in the half-accessed cell can be as low as $15\mu \text {W}$ . The design principles established in this work will provide guidelines for future exploration of functional oxides for selector applications as well as for the optimization of cross-point arrays.

P-Cu2O/SiOx/n-SiC/n-Si memory diode fabricated with room-temperature-sputtered n-SiC and SiOx

We investigated low-temperature fabrication processes for our previously proposed pn memory diode with a p-Cu2O/SiCxOy/n-SiC/n-Si structure having resistive nonvolatile memory and rectifying behaviors suitable for a cross-point memory array with the highest theoretical density. In previous fabrication processes, n-SiC was formed by sputtering at 1113 K, and SiCxOy and p-Cu2O were formed by the thermal oxidation of n-SiC and Cu at 1073 and 473 K, respectively. In this study, we propose a pn memory diode with a p-Cu2O/SiOx/n-SiC/n-Si structure, where n-SiC and SiOx layers are deposited by sputtering at room temperature. The proposed processes enable the fabrication of the pn memory diode at temperatures of not more than 473 K, which is used for the formation of p-Cu2O. This memory diode exhibits good nonvolatile memory and rectifying characteristics. These proposed low-temperature fabrication processes are expected to expand the range of fabrication processes applicable to current LSI fabrication processes.

Notice of Violation of IEEE Publication Principles: Overview of Selector Devices for 3-D Stackable Cross Point RRAM Arrays

Cross point RRAM arrays is the emerging area for future memory devices due to their high density, excellent scalability. Sneak path problem is the main disadvantage of cross point structures which needed to be overcome to produce real devices. Various self-rectifying cells like complementary resistive cell, hybrid RRAM cell, valence modulated conductive oxide RRAM and non-linear resistive memory with tunneling barrier, etc., are proposed to overcome the sneak path problem and to achieve the high density with good on/off ratio. However, it is challenging to fabricate the self-rectifying cells operating at low program/erase voltages with high non-linearity for both read and write operations and exhibiting good retention and endurance characteristics at the same time for a single device. 1S1R devices are more attractive than SRC due to large optimization possibilities to obtain better device performance as they have separate selector cell and memory cell which decouples the control parameters. Various kinds of selector devices like Si-based selector, metal-oxide based selector, threshold switch selector, mixed ionic-electronic conduction selector etc., are under intense research to obtain the best performance cross point memory devices. In this paper, we have briefly discussed about recent progress on various self-rectifying cells and selector devices for obtaining 3-D stackable cross point memory arrays.

Tunneling Electroresistance Effect with Diode Characteristic for Cross-Point Memory.

Cross-point memory architecture (CPMA) by using memristors has attracted considerable attention because of its high-density integration. However, a common and significant drawback of the CPMA is related to crosstalk issues between cells by sneak currents. This study demonstrated the sneak current free resistive switching characteristic of a ferroelectric tunnel diode (FTD) memristor for a CPMA by utilizing a novel concept of a ferroelectric quadrangle and triangle barrier switch. A FTD of Au/BaTiO3 (5 nm)/Nb-doped SrTiO3 (100) was used to obtain a desirable memristive effect for the CPMA. The FTD could reversibly change the shape of the ferroelectric potential from a quadrangle to a triangle. The effect included high nonlinearity and diode characteristics. It was derived from utilizing different sequences of carrier transport mechanisms such as the direct tunneling current, Fowler-Nordheim tunneling, and thermionic emission. The FTD memristor demonstrated the feasibility of sneak current-free high-density CPMA.

Nonlinear and multilevel resistive switching memory in Ni/Si3N4/Al2O3/TiN structures

In this letter, we extensively investigate the nonlinear resistive switching characteristics of Si3N4-based resistive random access memory (RRAM) devices that contain an Al2O3 tunnel barrier layer to alleviate sneak path currents in the cross-point array structure. When the compliance current (ICC) exceeds 1 mA, the Ni/Si3N4/TiN device shows both unipolar and bipolar switching with Ohmic characteristics in the low resistance state. Nonlinear resistive switching characteristics were observed for this device when ICC was ≤100 μA. We fabricated Si3N4/Al2O3 bilayer devices with different tunnel barrier layer thickness and characterized their nonlinear characteristics and failure resistance during the reset process. Furthermore, we obtained stable multiple resistance levels in the devices by varying ICC and the stop voltage for the set and reset switching, respectively. Our results suggest that an Al2O3 tunnel barrier layer embedded in Si3N4-based RRAM devices offers considerable potential to realize high-density cross-point memory array applications.

Disturbance characteristics of half-selected cells in a cross-point resistive switching memory array

Disturbance characteristics of cross-point resistive random access memory (RRAM) arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.

A Precise Model for Cross-Point Memory Array

A Precise Model for Cross-Point Memory Array

Threshold Selector With High Selectivity and Steep Slope for Cross-Point Memory Array

In this letter, we demonstrated a new type of threshold selector with excellent electrical characteristics for cross-point memory array. The proposed Ag/TiO2-based threshold selector device showed high selectivity ( $\sim 10^{\mathrm {\mathbf {7}}}$ ) and steep slope ( $ mV/decade). The observed threshold switching in programmable metallization cell device occurred due to the spontaneous rupturing of silver (Ag) filament. The Ag ionization to minimize the steric repulsion between Ag and surrounding TiO2 electrolyte was the main origin of the spontaneous rupture.

1D Selection Device Using Carbon Nanotube FETs for High-Density Cross-Point Memory Arrays

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1–7 pJ per bit and has a high programming endurance of up to $10^{6}\vphantom {\sum ^{R^{R}}}$ cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of $ are achieved.

Comprehensive analysis of electro thermally driven nanoscale insulator–metal transition SmNiO3-based selector for cross-point memory array

To implement a cross-point memory array successfully, it is highly required to develop nonlinear selector devices. Insulator–metal transition (IMT) devices are promising candidates for selector applications. Although IMT characteristics of SmNiO3 with a high transition temperature of 130 °C have already been reported, the film deposition conditions following high-pressure oxygen annealing at high temperatures are not practical for high-density memory applications. In this report, we propose a simple electrical method to form a localized IMT SmNiO3 region in a sputter-deposited SmNiOx film. The nanoscale IMT device formed by the electro thermal effect shows promising selector characteristics such as switching uniformity, switching endurance (>105 cycles), and high temperature stability. The feasibility of good selector characteristics is also investigated by serially connecting the selector device (SmNiO3 IMT) to a Ta/Ta2O5/Pt resistive random access memory (ReRAM) device.

A 4F2-cross-point phase change memory using nano-crystalline doped GeSbTe material

This paper reports on the use of nano-crystalline doped GeSbTe, or nano-GST, to fabricate a cross-point phase change memory with 4F2 cell size and test results obtained for it. We show the characteristics of a poly-Si diode select device with a high on–off ratio and data writing in a 4F2 memory cell array. The advantages of nano-GST over conventional GeSbTe are presented in terms of neighboring disturbance and 4F2 cross-point array formation. The memory cells’ high drivability, low power, and selective write and read performances are demonstrated. The scalability of the diode current density is also presented.

Impact of device size and thickness of Al2O 3 film on the Cu pillar and resistive switching characteristics for 3D cross-point memory application.

Impact of the device size and thickness of Al2O3 film on the Cu pillars and resistive switching memory characteristics of the Al/Cu/Al2O3/TiN structures have been investigated for the first time. The memory device size and thickness of Al2O3 of 18 nm are observed by transmission electron microscope image. The 20-nm-thick Al2O3 films have been used for the Cu pillar formation (i.e., stronger Cu filaments) in the Al/Cu/Al2O3/TiN structures, which can be used for three-dimensional (3D) cross-point architecture as reported previously Nanoscale Res. Lett.9:366, 2014. Fifty randomly picked devices with sizes ranging from 8 × 8 to 0.4 × 0.4 μm2 have been measured. The 8-μm devices show 100% yield of Cu pillars, whereas only 74% successful is observed for the 0.4-μm devices, because smaller size devices have higher Joule heating effect and larger size devices show long read endurance of 105 cycles at a high read voltage of -1.5 V. On the other hand, the resistive switching memory characteristics of the 0.4-μm devices with a 2-nm-thick Al2O3 film show superior as compared to those of both the larger device sizes and thicker (10 nm) Al2O3 film, owing to higher Cu diffusion rate for the larger size and thicker Al2O3 film. In consequence, higher device-to-device uniformity of 88% and lower average RESET current of approximately 328 μA are observed for the 0.4-μm devices with a 2-nm-thick Al2O3 film. Data retention capability of our memory device of >48 h makes it a promising one for future nanoscale nonvolatile application. This conductive bridging resistive random access memory (CBRAM) device is forming free at a current compliance (CC) of 30 μA (even at a lowest CC of 0.1 μA) and operation voltage of ±3 V at a high resistance ratio of >104.