Crossbar Design Research Articles

GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs

Recent advances in graph processing on FPGAs promise to alleviate performance bottlenecks with irregular memory access patterns. Such bottlenecks challenge performance for a growing number of important application areas like machine learning and data analytics. While FPGAs denote a promising solution through flexible memory hierarchies and massive parallelism, we argue that current graph processing accelerators either use the off-chip memory bandwidth inefficiently or do not scale well across memory channels. In this work, we propose GraphScale, a scalable graph processing framework for FPGAs. GraphScale combines multi-channel memory with asynchronous graph processing (i.e., for fast convergence on results) and a compressed graph representation (i.e., for efficient usage of memory bandwidth and reduced memory footprint). GraphScale solves common graph problems like breadth-first search, PageRank, and weakly connected components through modular user-defined functions, a novel two-dimensional partitioning scheme, and a high-performance two-level crossbar design. Additionally, we extend GraphScale to scale to modern high-bandwidth memory (HBM) and reduce partitioning overhead of large graphs with binary packing.

Spin device-based image edge detection architecture for neuromorphic computing

Artificial intelligence and deep learning today are utilized for several applications namely image processing, smart surveillance, edge computing, and so on. The hardware implementation of such applications has been a matter of concern due to huge area and energy requirements. The concept of computing in-memory and the use of non-volatile memory (NVM) devices have paved a path for resource-efficient hardware implementation. We propose a dual-level spin–orbit torque magnetic random-access memory (SOT-DLC MRAM) based crossbar array design for image edge detection. The presented in-memory edge detection algorithm framework provides spin-based crossbar designs that can intrinsically perform image edge detection in an energy-efficient manner. The simulation results are scaled down in energy consumption for data transfer by a factor of 8x for grayscale images with a comparatively smaller crossbar than an equivalent CMOS design. DLC SOT-MRAM outperforms CMOS-based hardware implementation in several key aspects, offering 1.53x greater area efficiency, 14.24x lower leakage power dissipation, and 3.63x improved energy efficiency. Additionally, when compared to conventional spin transfer torque (STT-MRAM and SOT-MRAM, SOT-DLC MRAM achieves higher energy efficiency with a 1.07x and 1.03x advantage, respectively. Further, we extended the image edge extraction framework to spiking domain where ant colony optimization (ACO) algorithm is implemented. The mathematical analysis is presented for mapping of conductance matrix of the crossbar during edge detection with an improved area and energy efficiency at hardware implementation. The pixel accuracy of edge-detected image from ACO is 4.9% and 3.72% higher than conventional Sobel and Canny based edge-detection.

Perancangan Mata Pisau pada Traktor Pemanen Jagung Menggunakan Solidwork

Corn is one of the plants in agriculture that is needed in the lives of people in West Sumatra. Based on data in 2020 the need for corn is in the range of 1.2 million tons. But what can be produced is 939,466 tons. Traditional corn harvesting technology is a problem that causes corn production is not maximized. Corn harvesting tractor is one of the innovations in agricultural technology. The most important unit of the harvesting machine is the blade. The success of the machine in the harvesting process is determined by the shape and strength of the blade. Experimental testing is expensive and time consuming. Therefore, this study examines the design and simulation of blade strength on corn harvesting tractors with Solidwork software. The simulation carried out is a static analytic structural simulation. The simulation results include von-mises stress, displacement and factor of safety. Stress on the crossbar design has a maximum value of 2.168e+07 N/m^2 at the shaft connection and the inside of the bearing, maximum displacement on the side of the blade tip with a value of 1.953e-01 mm and FoS with a value of 5.553e+04. In design S the maximum stress is 2.476e+07 N/m^2, the displacement on the side of the blade tip is 2.199e-01 mm and the FoS is 1.052e+04. Both designs were given the same material AISI 1045, a force load of 87.05 N and a torque load of 41.5 Nm. The design that is suitable for use is the S shape design based on the results of the simulation and the shape that is more suitable for the harvesting process.

Nonuniform Compressive Sensing via Ohmic Voltage Attenuation: A Memristive Crossbar Design Approach Leveraging Intrinsic Computation

Compressive sensing (CS) is a promising technique for transmitting signals in power-critical applications such as Internet of Things (IoT) devices. Nonuniform CS optimizes this process by adjusting sampling frequency based on the relative importance levels characterized by the signal of interest. Recent advances have yielded energy-efficient hardware implementations of CS sampling, leveraging spin-based crossbar architectures for in-memory vector-matrix multiplication and through the use of probabilistic bit (p-bit) devices to generate tunable random outputs for writing the array. Thus, a region of interest is generated via column-ordered density of on-state devices. Herein, we propose a simple design for supplying inputs to the p-bit devices, based on Ohmic voltage attenuation occurring along the word lines of the crossbar array. The technique embeds some required computations to be conducted intrinsically by the cross-points of the memristive array, thus bypassing overheads of conventional instruction execution and eliminating the need for costly hardware components, such as lookup tables (LUTs) and data converters. The design is shown to be robust for various array sizes and parasitics while generating the appropriate tuning signals within a single clock cycle duration of 1.6 ns, and at an energy overhead of 333 fJ. Compared with a standard approach using LUTs and digital to-analog converters, the design herein achieves a 583-fold reduction in energy and 23-fold reduction in transistor count.

A new nano-structure design of a 2 × 2 crossbar switch based on quantum dots for a nano-communication network

One of the novel nano-domain computing structures is Quantum-dot Cellular Automata (QCA). QCA is an evaluation paradigm that does not utilize transistors and could be a viable replacement for CMOS-based technologies. It is one of the most promising nano-devices aimed at replacing CMOS technology. The tunneling of electrons with a particular voltage within the quantum cell is used to execute QCA. On the other hand, implementing hardware communication in the nanoscale is critical and one of the most fundamental aspects of any nanotechnology. Also, a switched network is considered a basic element in transmitting the input signal among diverse subscribers of a disseminated communication network. Crossbars are the leading and most important circuit for secure and fast communication at the nanoscale. However, in the designs that have been presented for this circuit up to now, some items such as low consumption cells, high speed, and low space have not been considered entirely. The main purpose of providing these circuits is to facilitate the process of nano-communication based on QCA with low cell consumption, low space, and high speed. Thus, in the present article, two designs are demonstrated for crossbar circuits depending on QCA. The first design is attained in an individual layer, and the second one is achieved in multi-layers. To design these circuits, multiplexer circuits are used. The simulation results using QCADesigner approved that the suggested crossbars work well and can be employed as a high-efficiency layout. The comparison outcomes illustrate that the suggested construction contains better efficiency regarding cell number, area, and clock cycle than previous proposals. Furthermore, the simulation findings demonstrate that the coplanar design improves cell numbers by about 17%. The multi-layer design improves cell number by around 7%, compared to the best-presented QCA crossbar designs. Furthermore, 51 QCA cells are employed in the suggested coplanar design, whereas 58 QCA cells are used in the multi-layer architecture. Additionally, the baseline network was created with 1319 cells and an area of 2.14 µm2 to demonstrate the effectiveness of circuits employing the provided crossbar switches.

Highly parallelized memristive binary neural network

At present, in the new hardware design work of deep learning, memristor as a non-volatile memory with computing power has become a research hotspot. The weights in the deep neural network are the floating-point number. Writing a floating-point value into a memristor will result in a loss of accuracy, and the writing process will take more time. The binarized neural network (BNN) binarizes the weights and activation values that were originally floating-point numbers to +1 and -1. This will greatly reduce the storage space consumption and time consumption of programming the resistance value of the memristor. Furthermore, this will help to simplify the programming of memristors in deep neural network circuits and speed up the inference process. This paper provides a complete solution for implementing memristive BNN. Furthermore, we improved the design of the memristor crossbar by converting the input feature map and kernel before performing the convolution operation that can ensure the sign of the input voltage of each port constant. Therefore, we do not need to determine the sign of the input voltage required by the port in advance which simplifies the process of inputting the feature map elements to each port of the crossbar in the form of voltage. At the same time, in order to ensure that the output of the current convolution layer can be directly used as the input of the next layer, we have added a corresponding processing circuit, which integrates batch-normalization and binarization operations.

Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL

A great deal of effort has recently been devoted to extending the usage of memristor technology from memory to computing. Memristor-based logic design is an emerging concept that targets efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor–CMOS logic family. MRL requires an efficient design strategy that takes into consideration the implementation phase. This paper presents a novel MRL-based crossbar design: X-MRL. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder. The design is presented with its layout and corresponding simulation results using the Cadence Virtuoso toolset and CMOS 65nm process. The comparison with a pure CMOS implementation is promising in terms of the area, as our approach exhibits a 44.79% area reduction. Moreover, the combined Energy.Delay metric demonstrates a significant improvement (between ×5.7 and ×31) with respect to the available literature.

Design Exploration of ReRAM-Based Crossbar for AI Inference

ReRAM-based crossbar designs utilizing mixed-signal implementation has gained importance due to their low power, small size, low cost, and high throughput especially for multiply-and-add operations in AI-related applications. This paper provides a framework with associated code for analyzing the impact of ReRAM device variation and post-training analog conductance quantization that has not been fully explored for pre-trained network accelerators. A detailed study with end-to-end implementation is presented, ranging from mapping the pre-trained DNN weights to quantized crossbar conductance values and into final classification with the presence of variation. Monte Carlo analysis was performed to better analyze the impact of the different parameters on the final accuracy without being device-specific. The work assumes different conductance value variations, different conductance dynamic ranges, and various device quantization levels (QLs). MNIST and CIFAR-10 data sets were used in this study for ANN and CNN, respectively. Results show that for simple ANN, the accuracy drop due to quantization was ~ 2% at 64-QLs. While for CNN, the decrease in classification accuracy was around 10% with the same number of levels. Moreover, weight variation might cause a ~ 5% and ~ 8% drop in classification accuracy for ANN with 5% and CNN with 3% variation, respectively. The study confirms that increasing the number of levels with small variation results in near-optimal accuracy. However, the increase in accuracy saturates at an upper limit. The amount of distortion propagated through the layers is different in the two cases. It is dependent on the complexity of input data and network structure, such as the size of the neurons in each layer, the number of layers, and the number of channels and filters at each stage. This contribution is the first to provide the framework to explore the implication that emphasizes on device-independent post-training DNN quantization and weight variation on classification accuracy. This helps explore design trade-offs especially for edge devices in cases where there is no access to the training set to the end-user due to security or cost issues for pre-trained networks.

Design and Fabrication of Flow-Based Edge Detection Memristor Crossbar Circuits1

We design and fabricate a flow-based circuit for edge detection in images that exploits device-level parallelism in nanoscale memristor crossbars. In our approach, a corpus of human-labeled edges in BSDS500 images is used to learn an edge detection function with ternary values: true, false, and don’t-care. A Boolean crossbar design implementing an approximation of this ternary function using in-memory flow-based computing is then obtained using a massively parallel simulated annealing search executed on GPUs. We demonstrate the success of our approach by fabricating the memristor circuit on a 300mm wafer platform using a custom 65nm CMOS/ReRAM process technology. We demonstrate that our flow-based computing approach is either faster, more energy-efficient or produces fewer incorrect edges than other competing approaches. We show that our design has power and area requirements that are 3.3x and 2.5x lower, respectively, than the previous state-of-the-art.

Exploiting In-Memory Data Patterns for Performance Improvement on Crossbar Resistive Memory

Resistive memory (ReRAM) has emerged as a promising nonvolatile memory technology that may replace a significant portion of DRAM in future computer systems. ReRAM has many advantages, such as high density, low standby power, and good scalability. When adopting crossbar architecture, ReRAM cell can achieve the smallest theoretical size in fabrication, which is ideal for constructing dense memory with large capacity. However, crossbar cell structure suffers from a variety of reliability issues, which come from large voltage drops on long wires. To ensure operation reliability, ReRAM writes conservatively use the worst-case access latency of all cells in ReRAM arrays, which leads to significant performance degradation and dynamic energy waste. In this article, we study the correlation between the ReRAM cell switching latency and the number of cells in low-resistance state (LRS) along bitlines, and propose to dynamically speed up write operations based on bitline data patterns, i.e., the number of LRS cells presented in bitlines. We leverage the intrinsic in-memory processing capability of ReRAM crossbar and propose a low-overhead runtime profiler that effectively tracks the data patterns in different bitlines. To achieve further write latency reduction, we employ data compression and row address dependent memory data layout to reduce the numbers of LRS cells on bitlines. Moreover, we further present two optimization techniques, i.e., selective profiling and fine-grained profiling, to mitigate energy overhead brought by bitline data patterns tracking. The experimental results show that, on average, our design improves system performance by 20.5% and 14.2%, and reduces memory dynamic energy by 20.3% and 12.6%, compared to the baseline and the state-of-the-art crossbar design, respectively.

Design and ray tracing of multifaceted Scheffler reflector with novel crossbars

In this paper, a detailed design methodology of a novel and simple crossbar design for error-free Scheffler reflector profile is presented. The present work is undertaken to improve the existing crossbar design, which requires a three-point circular approximation of original elliptical crossbars. This approximation introduces a small error in the Scheffler profile. The proposed new crossbars are part of circles formed by the interception of a horizontal plane with paraboloid leading to an error-free Scheffler profile. Implicit equations involving various design parameters are solved iteratively and the prediction equations have been developed for inclination angle as a function of non-dimensional aperture radius and x-intercept as a function of inclination angle. Design charts for selecting radius, width and length of novel crossbars have also been developed. In addition, sections on seasonal tracking and reflector surface optimization and ray tracing are included with a focus on mirror (facet) size selection, arrangement of mirrors to avoid wrinkling in Scheffler profile, effect of mirror size on focus, focal shift due to delay in seasonal adjustments and the tracking mechanism for achieving fixed focus throughout the year. A MATLAB code for ray tracing of multifaceted Scheffler reflector for seasonal variation is provided along with this paper.

Transparent and Self-Powered Multistage Sensation Matrix for Mechanosensation Application.

Electronic skin based on a multimodal sensing array is ready to detect various stimuli in different categories by utilizing highly sensitive materials, sophisticated geometry designs, and integration of multifunctional sensors. However, it is still difficult to distinguish multiple and complex mechanical stimuli in a local position by conventional multimodal E-skin, which is significantly important in the signals' feedback of robotic fine motions and human-machine interactions. Here, we present a transparent, flexible, and self-powered multistage sensation matrix based on piezoelectric nanogenerators constructed in a crossbar design. Each sensor cell in the matrix comprises a layer of piezoelectric polymer sandwiched between two graphene electrodes. The simple lamination design allows sequential multistage sensation in one sensing cell, including compressive/tensile strain and detaching/releasing area. Further structure engineering on PDMS substrate allows the sensor cell to be highly sensitive to the applied pressures, representing the minimum sensing pressure below 800 Pa. As the basic combinations of compressive/tensile strains or detaching/releasing represent individual output signals, the proposed multistage sensors are capable of decoding to distinguish external complex motions. The proposed self-powering multistage sensation matrix can be used universally as an autonomous invisible sensory system to detect complex motions of the human body in local position, which has promising potential in movement monitoring, human-computer interaction, humanoid robots, and E-skins.

CLAP-NET: Bandwidth adaptive optical crossbar architecture

While the number of processing cores placed on individual silicon dies climbs towards hundreds, and even thousands of cores, there is growing demand for efficient and scalable on-chip interconnects. Offering many advantages over metallic interconnects, nanophotonic interconnects enable new design possibilities, however, nanophotonic interconnects also require an off-chip laser source, which is often wasted to insertion losses and periods of low network activity. We present a new optical crossbar architecture that leverages capabilities of nanophotonics to provide high-performance inter-core communication while maximizing utilization of the laser power by means of dynamic bandwidth and laser power reconfiguration schemes. We compare our architecture with other proposed optical crossbar designs according to power consumption, throughput, and latency. We evaluate the network using synthetic patterns to show approximately a 13% improvement in throughput can be achieved compared to other optical crossbar designs, and a 92% improvement compared to a conventional electrical flattened butterfly architecture.

More is Less, Less is More

Molecular-scale Network-on-Chip (mNoC) crossbars use quantum dot LEDs as an on-chip light source, and chromophores to provide optical signal filtering for receivers. An mNoC reduces power consumption or enables scaling to larger crossbars for a reduced energy budget compared to current nanophotonic NoC crossbars. Since communication latency is reduced by using a high-radix crossbar, minimizing power consumption becomes a primary design target. Conventional Single Writer Multiple Reader (SWMR) photonic crossbar designs broadcast all packets, and incur the commensurate required power, even if only two nodes are communicating. This paper introduces power topologies, enabled by unique capabilities of mNoC technology, to reduce overall interconnect power consumption. A power topology corresponds to the logical connectivity provided by a given power mode. Broadcast is one power mode and it consumes the maximum power. Additional power modes consume less power but allow a source to communicate with only a statically defined, potentially non-contiguous, subset of nodes. Overall interconnect power is reduced if the more frequently communicating nodes use modes that consume less power, while less frequently communicating nodes use modes that consume more power. We also investigate thread mapping techniques to fully exploit power topologies. We explore various mNoC power topologies with one, two and four power modes for a radix-256 SWMR mNoC crossbar. Our results show that the combination of power topologies and intelligent thread mapping can reduce total mNoC power by up to 51% on average for a set of 12 SPLASH benchmarks. Furthermore performance is 10% better than conventional resonator-based photonic NoCs and energy is reduced by 72%.

More is Less, Less is More

Molecular-scale Network-on-Chip (mNoC) crossbars use quantum dot LEDs as an on-chip light source, and chromophores to provide optical signal filtering for receivers. An mNoC reduces power consumption or enables scaling to larger crossbars for a reduced energy budget compared to current nanophotonic NoC crossbars. Since communication latency is reduced by using a high-radix crossbar, minimizing power consumption becomes a primary design target. Conventional Single Writer Multiple Reader (SWMR) photonic crossbar designs broadcast all packets, and incur the commensurate required power, even if only two nodes are communicating. This paper introduces power topologies, enabled by unique capabilities of mNoC technology, to reduce overall interconnect power consumption. A power topology corresponds to the logical connectivity provided by a given power mode. Broadcast is one power mode and it consumes the maximum power. Additional power modes consume less power but allow a source to communicate with only a statically defined, potentially non-contiguous, subset of nodes. Overall interconnect power is reduced if the more frequently communicating nodes use modes that consume less power, while less frequently communicating nodes use modes that consume more power. We also investigate thread mapping techniques to fully exploit power topologies. We explore various mNoC power topologies with one, two and four power modes for a radix-256 SWMR mNoC crossbar. Our results show that the combination of power topologies and intelligent thread mapping can reduce total mNoC power by up to 51% on average for a set of 12 SPLASH benchmarks. Furthermore performance is 10% better than conventional resonator-based photonic NoCs and energy is reduced by 72%.

Segmented Optimization Design of Aluminum Alloy Goal Crossbar Based on FEM

Aluminum alloy goal crossbar (crossbar for short) as an essential part of soccer goals, according to practical needs, needs to be designed in other ways. So the segmented optimization design of crossbar has been proposed.This paper proposes that cut off crossbar from the middle first, then use an iron core turning the segmented crossbar into a whole part again when used. By means of parametric modeling in AutoCAD and SolidWorks and finite element analysis in MARC, the feasibility of the optimization design has been demonstrated. Finally, the paper comes to a conclusion via the way of experimental test.

Cross-Bar Design of Nano-Vacuum Triode for High-Frequency Applications

In this letter, a new nano-vacuum triode based on carbon nanotubes (CNTs) has been designed. The use of CNTs as emitters with their extremely high aspect ratio and their characteristics to be patterned in specific emitting areas allowed the realization of a cross-bar geometry for which the transconductance is maximized and the grid-cathode capacitance is reduced. This allowed us to achieve a device cutoff frequency of 156 GHz, which is well beyond the state of the art.

Swizzle-Switch Networks for Many-Core Systems

This work revisits the design of crossbar and high-radix interconnects in light of advances in circuit and layout techniques that improve crossbar scalability, obviating the need for deep multi-stage networks. We employ a new building block, the Swizzle-Switch-an energy and area-efficient switching element that can readily scale to radix 64-that has recently been validated via silicon test chips in 45 nm technology. We evaluate the Swizzle-Switch as both the high-radix building block of a Flattened Butterfly and as a single-stage interconnect, the Swizzle-Switch Network. In the process we address the architectural and layout challenges associated with centralized crossbar systems. Compared to a conventional Mesh, the Flattened Butterfly provides a 15% performance improvement with a 2.5× reduction in the standard deviation of on-chip access times. The Swizzle-Switch Network achieves further gains, providing a 21% improvement in performance, a 3× reduction in on-chip access variability, a 33% reduction in interconnect power, and a 25% reduction in total system energy while only increasing chip area by 7%. Finally, this paper details a 3-D integrated version of the Swizzle-Switch Network, showing up to a 30% gain in performance over the 2-D Swizzle-Switch Network for benchmarks sensitive to interconnect latency. One major concern with 3-D designs is thermal dissipation. We show through detailed thermal analysis that with the highly energy-efficient Swizzle-Switch Network design that the thermal budget is well within that of passive cooling solutions.

Crossbar NoCs Are Scalable Beyond 100 Nodes

We describe the design and layout of a radix-128 crossbar in 90 nm CMOS. The data path is 32 bits wide and runs at 750 MHz using a three-stage pipeline, while fitting in a silicon area as small as 6.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> by filling it at the 90% level. The control path occupies 7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> next to the data path by filling it at 35% level, and reconfigures the data path once every three clock cycles. Next, we arrange 128 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> “user tiles” around the crossbar, forming a 150 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die, and we connect all tiles to the crossbar via global links running on top of the tiles. Including the overhead of repeaters and flip flops on global links, the area cost of the crossbar is 11% of the die. Thus, we prove that crossbar networks-on-chips (NoCs) are small enough for radices exceeding by far the few tens of ports, that were believed to be the practical limit up to now, and reaching above 100 ports. We also attempt a first-order comparison between our crossbar and a model of a popular mesh NoC, and we find that our crossbar NoC increases performance when traffic is global and stressed, at the cost of worse performance when traffic is local and benign. Finally, we present an experimental cost analysis showing that crossbar area practically grows as <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> ), as all wiring of the crossbar fits over its standard cells, while crossbar delay grows as O( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> √ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> ) , as wire length increases with the perimeter of the crossbar.

Development of room temperature crossbar-H-mode cavities for proton and ion acceleration in the low to medium beta range

The crossbar $H$-mode (CH) cavity is an accelerating structure operated in the ${H}_{21(0)}$ mode. The robustness of the crossbar geometry allows one to realize room temperature as well as superconducting linac cavities. The shunt impedance characteristics of this structure are attractive to develop proton and heavy ion linacs in the low and medium beta range. A first room temperature eight-cell prototype has proven the feasibility of the crossbar design in terms of mechanical construction, copper plating, and cooling. An innovative rf coupling concept has been developed where two CH cavities are connected by a two gap ${E}_{010}$-mode resonator which, at the same time, provides transverse focusing by a quadrupole triplet. The concept has been applied in the design of the new FAIR proton linac and a scaled model of the second cavity of this injector has been built and tested too. The full scale prototype is now under construction at the University of Frankfurt. In this paper, the room temperature CH cavity development as well as the general layout of the FAIR proton injector (70 MeV, 325 MHz, 70 mA) is presented and discussed.